Method for minimizing false detection of states in flash memory devices
View Patent ↗The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
1. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for minimizing leakage current when detecting states of memory cells comprising:
determining a selected bit line that is associated with a column of memory cells; and
biasing a group of word lines at a negative voltage to limit leakage current contributions from associated memory cells in said column of memory cells when performing a verify operation, wherein said memory cells are coupled to said group of word lines, and wherein said negative voltage is selected from a voltage between −0.5 volts to −2.0 volts, wherein said verify operation comprises an erase verify operation comprising:
determining a selected memory cell in said column of memory cells, said selected memory cell associated with said selected bit line, and a selected word line that is not part of said group of word lines; and
biasing said selected word line at approximately 3 volts;
biasing said selected bit line at approximately 0.65 volts; and
floating remaining bit lines.
2. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for minimizing leakage current when detecting states of memory cells comprising:
determining a selected bit line that is associated with a column of memory cells; and
biasing a group of word lines at a negative voltage to limit leakage current contributions from associated memory cells in said column of memory cells when performing a verify operation, wherein said memory cells are coupled to said group of word lines, and wherein said negative voltage is selected from a voltage between −0.5 volts to −2.0 volts, wherein said verify operation comprises an automatic program disturb after erase (APDE) verify operation comprising:
biasing all word lines at said negative voltage when performing an APDE verify operation on said column of memory cells;
biasing said selected bit line at approximately 0.65 volts; and
floating remaining bit lines.
3. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for minimizing leakage current when detecting states of memory cells comprising:
determining a selected bit line that is associated with a column of memory cells; and
biasing a group of word lines at a negative voltage to limit leakage current contributions from associated memory cells in said column of memory cells when performing a verify operation, wherein said memory cells are coupled to said group of word lines, and wherein said negative voltage is selected from a voltage between −0.5 volts to −2.0 volts, wherein said verify operation comprises a soft program verify operation comprising:
after performing a soft program operation of a memory cell that is over-erased in said column of memory cells, biasing a selected word line at approximately 2.6 volts, wherein said memory cell is coupled to said selected word line that is not part of said group of word lines;
biasing said selected bit line at approximately 0.65 volts; and
floating remaining bit lines.
4. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for minimizing leakage current when detecting states of memory cells comprising:
determining a selected bit line that is associated with a column of memory cells; and
biasing a group of word lines at a negative voltage to limit leakage current contributions from associated memory cells in said column of memory cells when performing a verify operation, wherein said memory cells are coupled to said group of word lines, and wherein said negative voltage is selected from a voltage between −0.5 volts to −2.0 volts, wherein said verify operation comprises a program verify operation comprising:
after performing a program operation of a memory cell in said column of memory cells, biasing a selected word line at approximately 5.2 volts, wherein said memory cell is coupled to said selected word line that is not part of said group of word lines;
biasing said selected bit line at approximately 0.65 volts; and
floating remaining bit lines.
5. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for detecting proper erasure of a memory cell comprising:
determining a selected memory cell in a column of memory cells, said selected memory cell associated with a selected word line and a selected bit line; and
biasing unselected word lines at a negative voltage to limit leakage current contributions from unselected memory cells in said column of memory cells when performing an erase verify operation on said selected memory cell, wherein said negative voltage is selected from a voltage between −0.5 volts to −2.0 volts;
selecting another column of memory cells, said another column of memory cells associated with another selected bit line; and
biasing all word lines at said negative voltage when performing an APDE verify operation on said another column of memory cells.
6. The method of claim 5 , further comprising:
before said determining a selected memory cell, performing an array wide erase operation on said array of memory cells.
7. The method of claim 5 , further comprising:
performing said erase verify operation on each memory cell in said array of memory cells;
performing another array wide erase operation when a failing memory cell in said array of memory cells is not properly erased and does not pass said erase verify operation; and
performing said performing said erase verify operation and said performing another array wide erase operation until all memory cells in said array of memory cells are erased.
8. The method of claim 5 , wherein said erase verify operation comprises:
biasing said selected word line at approximately 3 volts;
biasing said selected bit line at approximately 0.65 volts; and
floating remaining bit lines.
9. The method of claim 5 , further comprising:
performing said APDE verify operation on each column of memory cells in said array of memory cells;
performing an APDE operation when a failing memory cell in said array of memory cells does not pass said APDE verify operation and is not properly erased; and
performing said selecting another column of memory cells and said biasing all word lines at said negative voltage until all memory cells in said array of memory cells are properly erased.
10. The method of claim 5 , wherein said APDE verify operation further comprises:
biasing said another selected bit line at approximately 0.65 volts; and
floating remaining bit lines.
11. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for detecting proper erasure of a memory cell comprising:
a) performing a soft program operation of a selected memory cell in a column of memory cells, said selected memory cell associated with a selected bit line and a selected word line, wherein said soft program verify operation comprises:
biasing said selected word line at approximately 2.6 volts;
biasing said selected bit line at approximately 0.65 volts; and
floating remaining bit lines; and
b) biasing unselected word lines at a negative voltage to limit leakage current contributions from unselected memory cells in said column of memory cells when performing a soft program verify operation on said selected memory cell.
12. The method of claim 11 , wherein said selected memory cell is over-erased.
13. The method of claim 11 , further comprising:
before a), performing an array wide erase operation on said array of memory cells.
14. The method of claim 11 , wherein said
negative voltage is selected from a voltage between −0.5 volts to −2.0 volts.
15. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for detecting proper programming of a memory cell comprising:
a) performing a program operation of a selected memory cell in a column of memory cells, said selected memory cell associated with a selected bit line and a selected word line;
b) biasing unselected word lines at a negative voltage to limit leakage current contributions from unselected memory cells in said column of memory cells when performing a program verify operation on said selected memory cell, wherein said negative voltage is selected from a voltage between −0.5 volts to −2.0 volts, wherein said program verify operation comprises:
biasing said selected word line at approximately 5.2 volts;
biasing said selected bit line at approximately 0.65 volts; and
floating remaining bit lines.
16. In a non-volatile memory comprising at least one array of memory cells, a plurality of word lines arranged in a plurality of rows, a plurality of bit lines arranged in a plurality of columns, each of the memory cells comprising a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and capable of storing a respective bit, a method for detecting proper erasure of a memory cell comprising:
a) determining a selected memory cell in a column of memory cells, said selected memory cell associated with a selected word line and a selected bit line;
b) biasing unselected word lines at a negative voltage to limit leakage current contributions from unselected memory cells in said column of memory cells when performing an erase verify operation on said selected memory cell;
c) selecting another column of memory cells, said another column of memory cells associated with another selected bit line; and
d) biasing all word lines at said negative voltage when performing an APDE verify operation on said another column of memory cells, wherein said APDE verify operation further comprises:
e) biasing said another selected bit line at approximately 0.65 volts; and
f) floating remaining bit lines.
17. The method of claim 16 ,
further comprising
e) performing said APDE verify operation on each column of memory cells in said array of memory cells;
f) performing an APDE operation when a failing memory cell in said array of memory cells does not pass said APDE verify operation and is not properly erased; and
g) performing c) and d) until all memory cells in said array of memory cells are properly erased.