Multi-chip package with high-speed serial communications between semiconductor die
View Patent ↗A multi-chip package includes a package substrate. First and second semiconductor die are formed on the package substrate. The first and the second semiconductor die are configured to communicate with each other via a high-speed serial communications protocol.
1. A multi-chip package comprising:
a package substrate;
a first semiconductor die disposed on the package substrate comprising a first processor having a first set of speed and performance criteria associated therewith, the first semiconductor die further comprising first electronic circuitry in addition to the first processor; and
a second semiconductor die disposed on the package substrate comprising a second processor having a second set of performance and speed criteria associated therewith, the first set of criteria being different from the second set of criteria, the second semiconductor die further comprising second electronic circuitry in addition to the second processor;
wherein the first and the second semiconductor dice are communicatively coupled together by three or less communication links disposed on or within the multi-chip package, the first and second die being configured to communicate with one another by means of a high-speed serial communications protocol, the first processor and first electronic circuitry being optimized for performance in respect of the first set of criteria, the second processor and second electronic circuitry being optimized for performance in respect of the second set of criteria, wherein all communications between the first and the second semiconductor dice occur over the three or less communication links.
2. The multi-chip package of claim 1 , and further comprising a plurality of interconnection structures formed on a bottom surface of the package substrate.
3. The multi-chip package of claim 2 , wherein the interconnection structures are solder balls.
4. The multi-chip package of claim 1 , further comprising a plurality of interconnection structures for interconnecting the first and the second semiconductor dice to the package substrate.
5. The multi-chip package of claim 4 , wherein the interconnection structures comprise bond wires.
6. The multi-chip package of claim 1 , wherein the package substrate includes a set of conductive traces for carrying high speed serial communications between the first and the second semiconductor dice.
7. The multi-chip package of claim 1 , wherein the first and the second semiconductor dice are configured to communicate with each other via the high-speed serial communications protocol at a rate of at least one gigabits per second (Gbps).
8. The multi-chip package of claim 1 , wherein the first and the second semiconductor dice are configured to communicate with one another by means of the high-speed serial communications protocol at a rate of at least ten gigabits per second (Gbps).
9. The multi-chip package of claim 1 , wherein the first semiconductor further comprises at least one of a memory, phase-locked loop circuitry, input/output circuitry, and topic circuitry.
10. The multi-chip package of claim 1 , wherein second semiconductor die further comprises at least one of a memory, phase-locked loop circuitry, input/output circuitry, and logic circuitry.
11. The multi-chip package of claim 1 , wherein the multi-chip package is configured in at least one of a stacked die configuration and a flip-chip configuration.
12. The multi-chip package of claim 1 , wherein the multi-chip package is a computing system, and wherein the first semiconductor die includes circuitry formed by a first silicon processing technology, the second semiconductor die includes circuitry formed by a second silicon processing technology, and wherein the first processing technology is different than the second processing technology.
13. The multi-chip package of claim 1 , further comprising input/output circuitry configured to manage communications between the multi-chip package and devices external thereto.