Multi-mode integrated circuit structure
View Patent ↗A multi-mode integrated circuit structure. In one embodiment, an integrated circuit structure includes a first die having at least one first component disposed on a face, the first die fabricated using a first process that is optimal for operating the component in an first mode and a second die stacked on the first die, the second die having at least one second component disposed on a face and the second die fabricated using a second process separate from the first process that is optimal for operating the second component in a second mode. As such, the integrated circuit structure provides an electronic device with a single integrated circuit structure for performing operations optimally in more than one mode, such as operations in enhancement mode and operations in depletion mode.
1. A unitary gallium arsenide monolithic microwave integrated circuit (MMIC) structure capable of operating in an enhancement/depletion (E/D) mode, comprising:
a first die comprising gallium arsenide and having at least a first electronic component disposed on a first face, the first die being fabricated using a first process that is optimal for operating the first electronic component in an enhancement mode;
a second die stacked on the first die, the second die comprising gallium arsenide and having at least a second electronic component disposed on a second face, the second die being fabricated using a second process different from the first process, the second process being optimal for operating the second electronic component in a depletion mode, and
an electrically isolating interconnect layer disposed between the first die and the second die, the interconnect layer being configured to electrically interconnect the first and second dice.
2. The MMIC integrated circuit structure of claim 1 wherein the second die is stacked on the first die such that the first face is adjacent to the second face.
3. The MMIC integrated circuit structure of claim 2 , wherein the interconnect layer further comprises electrically non-conductive interconnect spacers that provide electrical isolation between the first die and the second die.
4. The MMIC integrated circuit structure of claim 1 wherein the at least first electronic component and the at least second electronic component comprise field effect transistors.
5. The MMIC integrated circuit structure of claim 1 wherein the first die and the second die are stacked such that the combined height comprises a wafer-level height.
6. The MMIC integrated circuit structure of claim 1 , further comprising a third die stacked on the second die, the third die having at least a third electronic component disposed on a third face thereof, the third die being fabricated using a third process different from the first and second processes that is optimal for operating the third electronic component in a third mode.
7. The MMIC integrated circuit structure of claim 1 , further comprising a third die stacked adjacent to the second die, the third die having at least a third component disposed on a third face, the third die being fabricated using the first process, the second die being disposed between the first and third dies.
8. The MMIC integrated circuit structure of claim 1 , further comprising a third die stacked adjacent to the first die, the third die having at least a third component disposed on a third face, the third die being fabricated using the second process, the first die being disposed between the second and third dies.
9. A system, comprising:
(a) a unitary gallium arsenide monolithic microwave integrated circuit (MMIC) structure capable of operating in an enhancement/depletion (E/D) mode, comprising:
(i) a first die comprising gallium arsenide and having at least a first electronic component disposed on a first face, the first die being fabricated using a first process that is optimal for operating the component in an enhancement mode; and
(ii) a second die stacked on the first die, the second die comprising gallium arsenide and having at least a second electronic component disposed on a second face, the second die being fabricated using a second process different from the first process that is optimal for operating the second electronic component in a depletion mode;
(iii) an electrically isolating interconnect layer disposed between the first die and the second die, the interconnect layer being configured to electrically interconnect the first and second dice; and
(b) a first external component operably coupled to the MMIC integrated circuit structure, the external component being operable to pass a first signal to the first electronic component and to pass a second signal to the second electronic component.
10. The system of claim 9 , further comprising a second external component operably coupled to the MMIC integrated circuit structure, the second external component being operable to receive a first signal from the first electronic component and to receive a second signal from the second electronic component.
11. The system of claim 9 , further comprising a processor operably coupled to the MMIC integrated circuit structure and the first external component.
12. The system of claim 9 wherein the MMIC integrated circuit structure further comprises an electronic amplifier component disposed on the first die.
13. The system of claim 9 wherein the MMIC integrated circuit structure further comprises an electronic switch component disposed on the second die.
14. The system of claim 9 wherein the MMIC integrated circuit structure further comprises an electronic switch control logic component disposed on the first die.
15. The system of claim 9 wherein the MMIC integrated circuit structure further comprises an electronic power control component disposed on the first die.
16. The system of claim 9 wherein the MMIC integrated circuit structure further comprises an electronic low-noise amplifier component disposed on the second die.
17. The system of claim 9 wherein the MMIC integrated circuit structure further comprises an electronic radio-frequency block component disposed on the second die.
18. The system of claim 9 wherein the MMIC integrated circuit structure further comprises an electronic current source component disposed on the second die.