Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing
View Patent ↗According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.
1. A structure comprising:
a substrate;
at least one memory cell situated on said substrate;
a first interlayer dielectric layer situated over said at least one memory cell and over said substrate;
an oxide cap layer situated on said first interlayer dielectric layer;
an etch stop layer situated on said oxide cap layer, said etch stop layer comprising TCS nitride;
wherein said etch stop layer blocks UV radiation.
2. The structure of claim 1 further comprising a second interlayer dielectric layer situated on said etch stop layer.
3. The structure of claim 2 further comprising an anti-reflective coating layer situated on said second interlayer dielectric layer.
4. The structure of claim 2 further comprising a trench situated in said second interlayer dielectric layer and said etch stop layer, said trench being filled with copper.
5. The structure of claim 1 wherein said oxide cap layer comprises undoped TEOS oxide.
6. The structure of claim 1 wherein said first interlayer dielectric layer comprises BPSG.
7. The structure of claim 1 wherein said at least one memory cell is a floating gate flash memory cell.
8. The structure of claim 1 wherein said at least one memory cell is a SONOS flash memory cell.
9. A structure comprising a substrate, at least one memory cell situated on said substrate, a first interlayer dielectric layer situated over said at least one memory cell and over said substrate, an oxide cap layer situated on said first interlayer dielectric layer, said structure being characterized in that:
an etch stop layer is situated on said oxide cap layer, said etch stop layer comprising TCS nitride, wherein said etch stop layer blocks UV radiation.
10. The structure of claim 9 further comprising a second interlayer dielectric layer situated on said etch stop layer.
11. The structure of claim 10 further comprising an anti-reflective coating layer situated on said second interlayer dielectric layer.
12. The structure of claim 10 further comprising a trench situated in said second interlayer dielectric layer and said etch stop layer, said trench being filled with copper.
13. The structure of claim 9 wherein said first interlayer dielectric layer comprises BPSG.
14. The structure of claim 9 wherein said at least one memory cell is selected from the group consisting of a floating gate flash memory cell and a SONOS flash memory cell.
15. A method comprising steps of:
depositing a first interlayer dielectric layer over at least one memory cell situated on a substrate;
depositing an oxide cap layer on said first interlayer dielectric layer;
depositing an etch stop layer on said oxide cap layer, said etch stop layer comprising TCS nitride;
wherein said etch stop layer blocks UV radiation.
16. The method of claim 15 further comprising a step of depositing a second interlayer dielectric layer on said etch stop layer.
17. The method of claim 16 further a step of depositing an anti-reflective coating layer on said second interlayer dielectric layer.
18. The method of claim 16 further comprising steps of:
etching a trench in said second interlayer dielectric layer and said etch stop layer;
filling said trench with copper.
19. The method of claim 15 wherein said first interlayer dielectric layer comprises BPSG.
20. The method of claim 15 wherein said at least one memory cell is selected from the group consisting of a floating gate flash memory cell and a SONOS flash memory cell.