IP Library Granted Patent US 7,173,505
Granted Patent B2
US 7,173,505 · App. 10/842,825 · Granted Feb 6, 2007

Tuning RF circuits using switched inductors provided in a monolithic integrated circuit

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Quick Facts
Patent No.
US 7,173,505
App. No.
10/842,825
Granted
Feb 6, 2007
Kind
B2
Abstract

A Radio Frequency (RF) circuit includes an active portion and a tuned portion. The active portion receives an RF signal and that operates upon the RF signal. The tuned portion couples to the active portion and includes a first inductor, a second inductor, and a switch. When the switch is closed, the second inductor couples to the first inductor and the tuned portion has first tuning characteristics. When the switch is open, the second inductor is decoupled from the first inductor and the tuned portion has second tuning characteristics. The tuned portion may include lumped or parasitic capacitance. The tuned portion alternately includes an inductor having a first terminal, a second terminal, an intermediate tap, and a switch that couples between the second terminal and the intermediate tap. When the switch is closed the tuned portion has first tuning characteristics and when the switch is open, the tuned portion has second tuning characteristics.

Claims (52)

1. A Radio Frequency (RF) circuit comprising:

an active portion that includes at least one transconductance transistor to convert an input voltage signal to a current signal, the active portion provided in a monolithic integrated circuit; and

a tuned portion coupled to the active portion to receive the current signal and to generate a tuned output signal at an output node, the tuned portion comprising:

a first inductor;

a second inductor; and

a switch coupled to the second inductor, the switch provided in the monolithic integrated circuit, wherein when the switch is closed the second inductor couples to the first inductor and the tuned portion has a first tuning characteristic, and wherein when the switch is open the second inductor is decoupled from the first inductor and the tuned portion has a second tuning characteristic.

2. The RF circuit of claim 1 , wherein the tuned portion further comprises a capacitance coupled to the first inductor.

3. The RF circuit of claim 1 , wherein:

when the switch is closed the RF circuit has a maximum gain at a first frequency; and

when the switch is open, the RF circuit has a maximum gain at a second frequency.

4. The RF circuit of claim 1 , wherein the switch comprises a PMOS transistor.

5. The RF circuit of claim 1 , wherein the switch comprises a series combination of an NMOS transistor and a dc-blocking capacitor.

6. The RF circuit of claim 1 , wherein the first and second inductors are provided in the monolithic integrated circuit.

7. The RF circuit of claim 1 ,

wherein at least one of the first inductor and the second inductor of the tuned portion are provided external to the monolithic integrated circuit.

8. The RF circuit of claim 1 , wherein:

the first tuning characteristic corresponds to a maximum impedance at the output node at a first frequency; and

the second tuning characteristic corresponds to a maximum impedance at the output node at a second frequency.

9. A Radio Frequency (RF) circuit comprising:

an active portion that includes at least one transconductance transistor to convert an input voltage signal to a current signal, the active portion provided in a monolithic integrated circuit; and

a tuned portion coupled to the active portion to receive the current signal and to generate a tuned output signal at an output node, the tuned portion comprising:

an inductor having a first terminal, a second terminal, and an intermediate tap; and

a switch provided in the monolithic integrated circuit and coupled between the second terminal and the intermediate tap, wherein when the switch is closed the tuned portion has a first tuning characteristic, and wherein when the switch is open the tuned portion has a second tuning characteristic.

10. The RF circuit of claim 9 , wherein the tuned portion further comprises at least one capacitor coupled to the inductor.

11. The RF circuit of claim 9 , wherein:

when the switch is closed the RF circuit has a maximum gain at a first frequency; and

when the switch is open, the RF circuit has a maximum gain at a second frequency.

12. The RF circuit of claim 9 , wherein the switch comprises a PMOS transistor.

13. The RF circuit of claim 9 , wherein the switch comprises a series combination of an NMOS transistor and a dc-blocking capacitor.

14. The RF circuit of claim 9 , wherein the inductor is provided in the monolithic integrated circuit.

15. The RF circuit of claim 9 ,

wherein the inductor of the tuning tuned portion is provided external to the monolithic integrated circuit.

16. The RF circuit of claim 9 , wherein:

the first tuning characteristic corresponds to a maximum impedance at the output node at a first frequency; and

the second tuning characteristic corresponds to a maximum impedance at the output node at a second frequency.

17. A differential Radio Frequency (RF) circuit comprising:

a differential active portion that includes at least one pair of transconductance transistors to convert a differential input voltage signal to a differential current signal, the differential active portion provided in a monolithic integrated circuit; and

a differential tuned portion coupled to the differential active portion to receive the differential current signal and to generate a tuned differential output signal at differential output nodes, each differential side comprising:

a first inductor;

a second inductor; and

a switch coupled to the second inductor, the switch provided in the monolithic integrated circuit, wherein when the switch is open the second inductor couples in series with the first inductor and the tuned portion has a first tuning characteristic, and wherein when the switch is closed the second inductor is decoupled from the first inductor and the tuned portion has a second tuning characteristic.

18. The differential RF circuit of claim 17 , wherein the switch comprises a PMOS transistor.

19. The differential RF circuit of claim 17 , wherein the switch comprises a series combination of an NMOS transistor and a dc-blocking capacitor.

20. The differential RF circuit of claim 17 , wherein the each side of the differential tuned portion further comprises at least one capacitor coupled to the corresponding first inductor.

21. A differential Radio Frequency (RF) circuit comprising:

a differential active portion that includes at least one pair of transconductance transistors to convert a differential input voltage signal to a differential current signal, the differential active portion provided in a monolithic integrated circuit; and

a differential tuned portion coupled to the differential active portion to receive the differential current signal and to generate a tuned differential output signal at differential output nodes, each differential side comprising:

an inductor having a first terminal, a second terminal, and an intermediate tap; and

a switch provided in the monolithic integrated circuit and coupled to the intermediate tap, wherein when the switch is open the tuned portion has a first tuning characteristic, and wherein when the switch is closed the tuned portion has a second tuning characteristic.

22. The differential RF circuit of claim 21 , wherein the switch comprises a PMOS transistor.

23. The differential RF circuit of claim 21 , wherein the switch comprises a series combination of an NMOS transistor and a dc-blocking capacitor.

24. The differential RF circuit of claim 21 , wherein the each side of the differential tuned portion further comprises at least one capacitor coupled to the corresponding first inductor.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2004
From: BEHZAD, ARYA REZA
To: BROADCOM CORPORATION
Reel/Frame 015321/0532 →