Delay locked loop circuit and method for testing the operability of the circuit
View Patent ↗A delay locked loop (DLL) circuit and method for testing the operability of the circuit utilizes one or more test signal sources and a test signal receiver to selectively transmit test signals, for example, static test signals, through an array of delay elements of the DLL circuit. The resulting output signals of the array are used to determine whether any delay element or a tap selector of the DLL circuit has malfunctioned, e.g., stuck-at fault.
1. A delay locked loop circuit comprising:
an input to receive an input clock signal;
a test signal source to provide a test signal;
a switching mechanism connected to the input and the test signal source, the switching mechanism being configured to selectively transmit one of the input clock signal and the test signal as a selected signal;
an array of delay elements connected to the switching mechanism to receive the selected signal, the delay elements being configured to selectively form a variable delay chain;
a tap selector connected to the array of delay elements, the tap selector being configured to provide tap signals to columns of delay elements of the array;
a test signal receiver connected to the array of delay elements to receive an output test signal from the array of delay elements, the output test signal providing information whether any of the delay elements is not properly operating; and
a second test signal source connected to the array of delay elements, the second test signal source being configured to provide a second test signal to the rows of the delay elements of the array, the second test signal being differant from the test signal of the test signal source.
2. The circuit of claim 1 further comprising a phase comparator connected to the switching mechanism and the array of delay elements to compare the selected signal from the switching mechanism and an output signal from the array of delay elements, the phase comparator being also connected to the tap selector to inform the tap selector when phases of the selected signal and the output signal are sufficiently synchronized.
3. The circuit of claim 1 wherein the test signal source, the second test signal source and the test signal receiver include flip-flops.
4. The circuit of claim 1 wherein the test signal source and the test signal receiver are implemented as a single flip-flop.
5. The circuit of claim 1 wherein the switching mechanism includes a multiplexer having two inputs and a single output.
6. The circuit of claim 1 wherein each delay element of the array includes a delay buffer having an input and an output and a multiplexer having inputs and an output, the input of the delay buffer being connected to one of the inputs of the multiplexer.
7. A delay locked loop circuit comprising:
an input to receive an input clock signal;
means for providing a test signals from a test signal source;
a switching mechanism connected to the input and the receiving means, the switching mechanism being configured to selectively transmit one of the input clock signal and the test signal as a selected signal;
an array of delay elements connected to the switching mechanism to receive the selected signal, the delay elements being configured to selectively form a variable delay chain;
a tap selector connected to the array of delay elements, the tap selector being configured to provide tap signals to columns of delay elements of the array;
means for receiving an output test signal from the array of delay elements, the output test signal providing information whether any of the delay elements is not properly operating; and
means for providing a second test signal from a second test signal source to the rows of the delay elements of the array, the second test signal being different from the test signal.
8. The circuit of claim 7 further comprising a phase comparator connected to the switching mechanism and the array of delay elements to compare the selected signal from the switching mechanism and an output signal from the array of delay elements, the phase comparator being also connected to the tap selector to inform the tap selector when phases of the selected signal and the output signal are sufficiently synchronized.
9. The circuit of claim 7 wherein the means for proving the test signal, the means for providing the second test signal and the means for receiving the output test signal include flip-flops.
10. The circuit of claim 7 wherein the means for providing the test signal and the means for receiving the output test signals are implemented as a single flip-flop.
11. The circuit of claim 7 wherein the switching mechanism includes a multiplexer having two inputs and a single output.
12. The circuit of claim 7 wherein each delay element of the array includes a delay buffer having an input and an output and a multiplexer having inputs and an output, the input of the delay buffer being connected to one of the inputs of the multiplexer.
13. A method for testing the operability of a delay locked loop circuit, the method comprising:
controlling a tap selector of the delay locked loop circuit to apply tap signals to columns of an array of delay elements of the delay locked loop circuit to selectively set the delay elements to operating states such that a signal is expected to propagate from an input node of the array to an output node of the array along a signal path provided by the delay elements;
applying a test signal from a test signal source to the input node of the array of delay elements;
receiving an output test signal from the output node of the array of delay elements;
determining whether any of the delay elements is not properly operating using the output test signal;
applying a second test signal from a second test signal source to rows of the array of delay elements, the second test signal being different that the test signal;
controlling the tap selector of the delay locked loop circuit to apply different tap signals to the columns of the array of delay elements to selectively set the delay elements of each column to a particular operating state;
receiving a second output test signal from the output node of the array of delay elements;
determining whether the tap selector is not properly operating using the second output test signal; and
labeling the delay locked loop circuit as inoperable in response to the determining of whether any of the delay elements is not properly operating and the determining of whether the tap selector is not properly operating.
14. The method of claim 13 wherein the applying of the test signal includes controlling a flip-flop to provide the test signal to the input node of the array of delay elements.
15. The method of claim 13 wherein the applying of the test signal includes controlling a first flip-flop to provide the test signal to the input node of the array of delay elements, and wherein the applying of the second test signal includes controlling a second flip-flop to provide the second test signal to the rows of the array of delay elements.
16. The method of claim 13 wherein the controlling of the tap selector of the delay locked loop circuit to apply the different tap signals includes controlling the tap selector of the delay locked loop circuit to sequentially apply a unique tap signal to each column of the array of delay elements to sequentially set the delay elements of each column to a specific operating state.