IP Library Granted Patent US 6,891,418
Granted Patent B2
US 6,891,418 · App. 10/845,055 · Granted May 10, 2005

High speed flip-flop

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Quick Facts
Patent No.
US 6,891,418
App. No.
10/845,055
Granted
May 10, 2005
Kind
B2
Abstract

A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as the static latch. When the switches are closed, a second pair of back-to-back transistors is connected to the first pair so the two pairs acting together serve as a dynamic latch.

Claims (12)

1. A method for operating a latch in either a dynamic mode or a static mode, the method comprising:

permanently biasing first and second cross-coupled transistors of a first conductivity type so the first and second transistors alternately turn on and off responsive to input signals;

conditionally biasing third and fourth cross-coupled transistors of a second conductivity type so the third and fourth transistors alternately turn on and off responsive to input signals when bias is applied to the third and fourth transistors;

configuring the transistors so the first and third transistors turn on and off at the same time and the second and fourth transistors turn on and off at the same time when bias is applied to the third and fourth transistors, and

controlling the third and fourth transistors so alternatively bias is applied thereto in a static mode or withheld therefrom in a dynamic mode.

2. The method of claim 1 , in which the configuring operates the on transistors and the off transistors in the active bias region in the dynamic mode.

3. The method of claim 2 , in which the configuring operates the on transistors in saturation and the off transistors in cutoff in the static mode.

4. The method of claim 1 , in which the configuring operates the on transistors in saturation and the off transistors in cutoff in the static mode.

5. The method of claim 1 , in which the controlling switches the bias so it is alternatively applied to or withheld from the third and fourth transistors.

6. The method of claim 1 , in which the permanent biasing applies a positive bias to P conductivity type transistors.

7. The method of claim 6 , in which the conditionally biasing applies a negative bias to N conductivity type transistors.

8. The method of claim 1 , in which the conditionally biasing applies a negative bias to N conductivity type transistors.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →