Jitter producing circuitry and methods
To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).
1. A method of adding jitter to a clock signal comprising:
delaying successive cycles of the clock signal by a cyclically changing amount; and
cyclically changing the amount of delay by a plurality of unit delay increments, wherein said cyclically changing comprises controlling amplitude of the cyclically changing amount of delay by selecting a maximum number of the plurality of unit delay increments to cyclically change the amount of delay.
2. The method defined in claim 1 wherein the cyclically changing comprises:
controlling frequency of the cyclically changing amount of delay.
3. The method defined in claim 2 wherein the controlling frequency is at least partly responsive to frequency of the clock signal.
4. The method defined in claim 2 wherein controlling the frequency comprises:
selecting a rate for cyclically changing the amount of delay by the plurality of unit delay increments.
5. The method defined in claim 3 wherein the controlling frequency comprises:
dividing the frequency of the clock signal by a divisor parameter.
6. The method defined in claim 5 wherein the divisor parameter is variable.
7. The method defined in claim 1 wherein the controlling amplitude is at least partly responsive to an amplitude parameter.
8. The method defined in claim 7 wherein the amplitude parameter is variable.
9. Apparatus for adding jitter to a clock signal comprising:
means for delaying successive cycles of the clock signal by a cyclically changing amount; and
means for cyclically changing the amount of delay by a plurality of unit delay increments, wherein said means for cyclically changing comprises means for controlling amplitude of the cyclically changing amount of delay by means for selecting a maximum number of the plurality of unit delay increments to cyclically change the amount of delay.
10. The apparatus defined in claim 9 wherein the means for cyclically changing comprises:
means for controlling frequency of the cyclically changing amount of delay.
11. The apparatus defined in claim 10 wherein the means for controlling frequency is at least partly responsive to frequency of the clock signal.
12. The apparatus defined in claim 10 wherein the means for controlling frequency comprises:
means for selecting a rate for cyclically changing the amount of delay by the plurality of unit delay increments.
13. The apparatus defined in claim 11 wherein the means for controlling frequency comprises:
means for dividing the frequency of the clock signal by a divisor parameter.
14. The apparatus defined in claim 13 wherein the divisor parameter is variable.
15. The apparatus defined in claim 9 wherein the means for controlling amplitude is at least partly responsive to an amplitude parameter.
16. The apparatus defined in claim 15 wherein the amplitude parameter is variable.
17. Apparatus for adding jitter to a clock signal comprising:
delay circuitry that delays successive cycles of the clock signal by a cyclically changing amount; and
control circuitry that cyclically changes the amount of delay by a plurality of unit delay increments, wherein said control circuitry comprises amplitude control circuitry that controls amplitude of the cyclically changing amount of delay having circuitry that selects a maximum number of the plurality of unit delay increments to cyclically change the amount of delay.
18. The apparatus defined in claim 17 wherein the control circuitry comprises:
frequency control circuitry that controls frequency of the cyclically changing amount of delay.
19. The apparatus defined in claim 18 wherein the frequency control circuitry is at least partly responsive to frequency of the clock signal.
20. The apparatus defined in claim 19 wherein the frequency control circuitry comprises:
frequency dividing circuitry that divides the frequency of the clock signal by a divisor parameter.
21. The apparatus defined in claim 20 wherein the divisor parameter is variable.
22. The apparatus defined in claim 18 wherein the frequency control circuit comprises:
circuitry that selects a rate for cyclically changing the amount of delay by the plurality of unit delay increments.
23. The apparatus defined in claim 17 wherein the amplitude control circuitry is at least partly responsive to an amplitude parameter.
24. The apparatus defined in claim 23 wherein the amplitude parameter is variable.
25. A method of adding jitter to a clock signal comprising:
delaying successive cycles of the clock signal by a cyclically changing amount using a plurality of unit delay elements connected in series, the number of unit delay elements being selectable and ranging from all to none of the plurality of unit delay elements, wherein the unit delay elements delay the successive cycles of the clock signal by cyclically changing the number of selected unit delay elements.
26. The method defined in claim 25 wherein the delaying comprises:
controlling frequency of the cyclically changing amount of delay.
27. The method defined in claim 26 wherein controlling the frequency comprises:
selecting a rate for cyclically changing the number of selected unit delay elements.
28. The method defined in claim 26 wherein the controlling frequency is at least partly responsive to frequency of the clock signal,.
29. The method defined in claim 28 wherein the controlling frequency comprises:
dividing the frequency of the clock signal by a divisor parameter.
30. The method defined in claim 29 wherein the divisor parameter is variable.
31. The method defined in claim 25 wherein the delaying comprises:
controlling amplitude of the cyclically changing amount of delay.
32. The method defined in claim 31 wherein controlling the amplitude comprises:
selecting a maximum number of selected unit delay elements to cyclically change the amount of delay.
33. The method defined in claim 31 wherein the controlling amplitude is at least partly responsive to an amplitude parameter.
34. The method defined in claim 33 wherein the amplitude parameter is variable.
35. Apparatus for adding jitter to a clock signal comprising:
means for delaying successive cycles of the clock signal by a cyclically changing amount using a plurality of unit delay means connected in series, the number of unit delay means being selectable and ranging from all to none of the plurality of unit delay means, wherein the unit delay means delay the successive cycles of the clock signal by cyclically changing the number of selected unit delay means.
36. The apparatus defined in claim 35 wherein the means for delaying comprises:
means for controlling frequency of the cyclically changing amount of delay.
37. The apparatus defined in claim 36 wherein the means for controlling the frequency comprises:
means for selecting a rate for cyclically changing the number of selected unit delay means.
38. The apparatus defined in claim 36 wherein the means for controlling frequency is at least partly responsive to frequency of the clock signal.
39. The apparatus defined in claim 38 wherein the means for controlling frequency comprises:
means for dividing the frequency of the clock signal by a divisor parameter,.
40. The apparatus defined in claim 39 wherein the divisor parameter is variable.
41. The apparatus defined in claim 35 wherein the means for delaying comprises:
means for controlling amplitude of the cyclically changing amount of delay.
42. The apparatus defined in claim 41 wherein the means for controlling the amplitude comprises:
means for selecting a maximum number of selected unit delay means to cyclically change the amount of delay.
43. The apparatus defined in claim 41 wherein the means for controlling the amplitude is at least partly responsive to an amplitude parameter.
44. The apparatus defined in claim 43 wherein the amplitude parameter is variable.
45. Apparatus for adding jitter to a clock signal comprising:
delay circuitry that delays successive cycles of the clock signal by a cyclically changing amount using a plurality of unit delay elements connected in series, the number of unit delay elements being selectable and ranging from all to none of the plurality of unit delay elements, wherein the unit delay elements delay the successive cycles of the clock signal by cyclically changing the number of selected unit delay elements.
46. The apparatus defined in claim 35 wherein the delay circuitry comprises:
frequency control circuitry that controls frequency of the cyclically changing amount of delay.
47. The apparatus defined in claim 36 wherein the frequency control circuitry comprises:
circuitry that selects a rate for cyclically changing the number of selected unit delay elements.
48. The apparatus defined in claim 36 wherein the frequency control circuitry is at least partly responsive to frequency of the clock signal.
49. The apparatus defined in claim 38 wherein the frequency control circuitry comprises:
frequency dividing circuitry that divides the frequency of the clock signal by a divisor parameter,.
50. The apparatus defined in claim 39 wherein the divisor parameter is variable.
51. The apparatus defined in claim 35 wherein the delay circuitry comprises:
amplitude control circuitry that controls amplitude of the cyclically changing amount of delay.
52. The apparatus defined in claim 41 wherein the amplitude control circuitry comprises:
amplitude selection circuitry that selects a maximum number of unit delay elements to cyclically change the amount of delay.
53. The apparatus defined in claim 41 wherein the amplitude control circuitry is at least partly responsive to an amplitude parameter.
54. The apparatus defined in claim 43 wherein the amplitude parameter is variable.