IP Library › Granted Patent US 7,026,848
Granted Patent B2
US 7,026,848 · App. 10/847,353 · Granted Apr 11, 2006

Pre-driver circuit

Assignee: Rambus Inc.
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Quick Facts
Patent No.
US 7,026,848
App. No.
10/847,353
Granted
Apr 11, 2006
Kind
B2
Abstract

A pre-driver circuit for use in high speed signaling systems is disclosed. In one particular exemplary embodiment, the pre-driver circuit may comprise an input transistor, an active load, a passive load, and a current source. The input transistor has a gate terminal, a current sinking terminal, and a current sourcing terminal. The active load has a control input coupled to the gate terminal of the input transistor, a current sourcing terminal coupled to the current sinking terminal of the input transistor, and a current sinking terminal. The passive load has a first terminal coupled to the current sinking terminal of the active load and a second terminal coupled to the current sourcing terminal of the active load. The current source is coupled to the current sourcing terminal of the input transistor.

Claims (32)

1. A pre-driver circuit comprising:

an input transistor having a gate terminal, a current sinking terminal, and a current sourcing terminal;

first active load having a control input coupled to the gate terminal of the input transistor, a current sourcing terminal coupled to the current sinking terminal of the input transistor, and a current sinking terminal;

a second active load having a control input coupled to the current sourcing terminal of the first active load and to the current sinking terminal of the input transistor, a current sinking terminal coupled to the current sinking terminal of the first active load, and a current sourcing terminal;

a passive load having a first terminal coupled to the current sourcing terminal of the first active load and a second terminal coupled to the current sourcing terminal of the second active load; and

a current source coupled to the current sourcing terminal of the input transistor.

2. The pre-driver circuit of claim 1 , wherein the input transistor is one of a MOS transistor and a bipolar transistor.

3. The pre-driver circuit of claim 2 , wherein the input transistor is an NMOS transistor.

4. The pre-driver circuit of claim 1 , wherein the first active load is one of a MOS transistor and a bipolar transistor.

5. The pre-driver circuit of claim 4 , wherein the first active load is a PMOS transistor.

6. The pre-driver circuit of claim 1 , wherein the passive load is a resistor device.

7. The pre-driver circuit of claim 1 , wherein the current source comprises a transistor controlled by a bias signal.

8. The pre-driver circuit of claim 1 , wherein the current sinking terminal of the first active load and the current sinking terminal of the second active load are coupled to a power supply.

9. The pre-driver circuit of claim 1 , wherein the second active load is one of a MOS transistor and a bipolar transistor.

10. The pre-driver circuit of claim 9 , wherein the second active load is a PMOS transistor.

11. The pre-driver circuit of claim 1 , wherein the input transistor is a first input transistor and the passive load is a first passive load, further comprising:

a second input transistor having a gate terminal, a current sinking terminal, and a current sourcing terminal;

a third active load having a control input coupled to the gate terminal of the second input transistor, a current sourcing terminal coupled to the current sinking terminal of the second input transistor, and a current sinking terminal;

a fourth active load having a control input coupled to the current sourcing terminal of the third active load and to the current sinking terminal of the second input transistor, a current sinking terminal coupled to the current sinking terminal of the third active load, and a current sourcing terminal;

a second passive load having a first terminal coupled to the current sourcing terminal of the third active load and a second terminal coupled to the current sourcing terminal of the fourth active load; and

wherein the current sourcing terminal of the second input transistor is coupled to the current sourcing terminal of the first input transistor.

12. The pre-driver circuit of claim 11 , wherein the second input transistor is one of a MOS transistor and a bipolar transistor.

13. The pre-driver circuit of claim 12 , wherein the second input transistor is an NMOS transistor.

14. The pre-driver circuit of claim 11 , wherein the third active load is one of a MOS transistor and a bipolar transistor.

15. The pre-driver circuit of claim 14 , wherein the third active load is a PMOS transistor.

16. The pre-driver circuit of claim 11 , wherein the second passive load is a resistor device.

17. The pre-driver circuit of claim 11 , wherein the current source comprises a transistor controlled by a bias signal.

18. The pre-driver circuit of claim 11 , wherein the current sinking terminal of the third active load and the current sinking terminal of the fourth active load are coupled to a power supply.

19. The pre-driver circuit of claim 11 , wherein the second active load is one of a MOS transistor and a bipolar transistor.

20. The pre-driver circuit of claim 19 , wherein the second active load is a PMOS transistor.

21. The pre-driver circuit of claim 11 , wherein the fourth active load is one of a MOS transistor and a bipolar transistor.

22. The pre-driver circuit of claim 21 , wherein the fourth active load is a PMOS transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2004
From: WANG, YUEYONG; SHI, XUDONG
To: RAMBUS INC.
Reel/Frame 015347/0784 →
Continuity (1)
Related Publication 20050258875A1 · Nov 24, 2005