Delta-sigma modulator
A Delta-Sigma modulator is disclosed, which has a Delta adder, a Sigma adder, a first latch, a second latch and a feedback generator, wherein the feedback generator provides a feedback signal to the Delta adder based on a pre-stage data signal provided by the first latch, so that the Delta adder provides a pre-stage addition signal. The Sigma adder performs an accumulation to provide an accumulative signal to the first latch, so that the first latch provides a pre-stage data signal to the second latch to enable the second latch to output a digital output signal.
1. A Delta-Sigma modulator, comprising:
a Delta adder, receiving a digital input signal and a feedback signal for performing an addition operation to provide a pre-stage addition signal;
a Sigma adder, coupled to the Delta adder for receiving the pre-stage addition signal and a pre-stage data signal, thereby performing a accumulation to provide a accumulative signal;
a first latch, coupled to the Sigma adder and receiving a clock signal and the accumulative signal respectively, thereby latching the accumulative signal or outputting the pre-stage data signal based on the clock signal;
a feedback generator, coupled to the first latch for receiving the pre-stage data signal and providing the feedback signal based on an adjustment signal; and
a second latch, coupled to the first latch and receiving the clock signal and the pre-stage data signal, thereby latching the pre-stage data signal or outputting a digital output signal based on the clock signal.
2. The Delta-Sigma modulator as claimed in claim 1 , further comprising a low pass filter coupled to the second latch for converting the digital output signal to an analog signal.
3. The Delta-Sigma modulator as claimed in claim 1 , further comprising a clamping unit connected between the Sigma adder and the first latch for clamping the accumulative signal, thereby scaling up the digital input signal.
4. The Delta-Sigma modulator as claimed in claim 1 , wherein the digital input signal is scaled up or down signal by a magnification factor of 2 Y /2 Z , where Y is the number of bits in the digital input signal and Z is the number of bits in the feedback signal.
5. The Delta-Sigma modulator as claimed in claim 1 , wherein the digital input signal is expressed by signed representation, and the digital input signal has a value in the range of −2 Y−1 ˜2 Y−1 −1 where Y is the number of bits in the digital input signal.
6. The Delta-Sigma modulator as claimed in claim 1 , wherein the feedback signal has a value of −2 Z−1 or 2 Z−1 −1, where Z is the number of bits in the feedback signal; when the pre-stage data signal received by the feedback generator is at low level, the feedback generator outputs 2 Z−1 −1 to the Delta adder; when the pre-stage data signal received by the feedback generator is at high level, the feedback generator outputs −2 Z−1 to the Delta adder.
7. The Delta-Sigma modulator as claimed in claim 1 , wherein the first latch and the second latch are D-type flip-flops.