Differential transistor pair
A differential transistor pair comprises a plurality of transistor cells in a substrate. Each cell comprises first drain regions at the respective edge of the cell, and a second drain region in between. Source regions are located between the respective first drain region and the second drain region. First gate regions are located between the respective first drain region and the source regions, and second gate regions are located between the source regions and the second drain region. The first drain regions of all cells are interconnected to a common first drain terminal, and the second drain region of all cells are interconnected to a common second drain terminal. The first gate regions of all cells are interconnected to a common first gate terminal, and the second gate regions of all cells are interconnected to a common second gate terminal.
1. A differential transistor pair comprising a first and second transistor, said first and second transistors comprising at least one transistor cell provided in a substrate, the at least one cell comprising:
a first and a second drain/collector region belonging to the first transistor of said differential transistor pair and arranged separated from each other,
a third drain/collector region belonging to the second transistor of said differential transistor pair, and arranged between said first and second drain/collector regions,
a first source/emitter region arranged between said first drain/collector region and said third drain/collector region, and a second source/emitter region arranged between said second drain/collector region and said third drain/collector region, said source/emitter regions being common to both transistors of the differential transistor pair,
a first and a second gate/base region belonging to the first transistor of said differential transistor pair, said first gate/base region being arranged between said first drain collector region and the first source/emitter region, and said second gate/base region being arranged between said second drain/collector region and the second source/emitter region, and
a third and a fourth gate/base region belonging to the second transistor of said differential transistor pair, said third gate/base region being arranged between said third drain/collector region and the first course/emitter region, and said fourth gate/base region being arranged between said third drain/collector region and the second source/emitter region.
2. The differential transistor pair as claimed in claim 1 , comprising a plurality of transistor cells, wherein
the first and second drain/collector regions of each of said plurality of transistor cells of said first transistor are interconnected to a common first drain/collector terminal,
the third drain/collector region of each of said plurality of transistor cells of said second transistor are interconnected to a common second drain/collector terminal,
the first and second gate/base regions of each of said plurality of transistor cells of said first transistor are interconnected to a common first gate/base terminal, and
the third and fourth gate/base regions of each of said plurality of transistor cells of said second transistor are interconnected to a common second gate/base terminal.
3. The differential transistor pair as claimed in claim 1 , for use in RF power amplifier applications.
4. The differential transistor pair as claimed in claim 1 , wherein said differential transistor pair is a differential LDMOS transistor pair or a differential bipolar junction transistor pair.
5. The differential transistor pair as claimed in claim 1 , wherein each of said first and second transistors has a finger type layout.