IP Library › Granted Patent US 7,215,266
Granted Patent B2
US 7,215,266 · App. 10/851,307 · Granted May 8, 2007

Hybrid DC offset cancellation scheme for wireless receiver

Assignee: Wionics Research
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Quick Facts
Patent No.
US 7,215,266
App. No.
10/851,307
Granted
May 8, 2007
Kind
B2
Abstract

Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.

Claims (23)

1. A system in a wireless receiver including DC offset cancellation, comprising:

a mixer receiving a high frequency signal and a local oscillator signal and providing a downconverted signal;

a variable amplifier receiving the downconverted signal and providing an amplified downconverted signal, the magnitude of amplification being based on a gain value associated with a selected discrete gain state of a plurality of discrete gain states each having an associated stored gain value;

a DC offset measurement circuit, in data communication with the variable amplifier, measuring DC offset for the selected discrete gain state and generating DC offset control information based on the measured DC offset;

a high pass filter coupled between the variable amplifier and the DC offset measurement circuit;

a memory storing the associated stored gain values, the associated stored gain values being affected by the DC offset control information; and

an automatic gain controller circuit selecting a discrete gate state from the plurality of the discrete gain states.

2. The system of claim 1 , wherein the DC offset measurement circuit comprises a Fast Fourier Transform (FFT) block.

3. The system of claim 1 , wherein the DC offset measurement circuit comprises a processor.

4. The system of claim 3 , wherein the processor performs a Fast Fourier Transform.

5. The system of claim 1 , wherein the DC offset measurement circuit updates the DC offset control information.

6. The system of claim 1 further comprising a digital-to-analog converter translating a bias signal associated with the gain value, the bias signal adjusting operation of the mixer.

7. A method of correcting DC offset, the method comprising:

receiving a radio frequency signal providing information in frames;

downconverting and amplifying the radio frequency signal, amplification of the radio frequency signal dependent on a gain state selected from a plurality of discrete gain states, each of the discrete gain states having an associated gain value;

providing the downconverted and amplified signal to a high pass filter with a switchable corner frequency, an output of the high pass filter coupled to an analog-to-digital converter to thereby digitize the downconverted, amplified, filtered signal;

setting the high pass filter to a first corner frequency; and

switching the high pass filter to a second corner frequency, lower than the first corner frequency, during reception of a frame.

8. The method of claim 7 further comprising:

opening a feedback loop of the high pass filter to form an all pass filter during reception of the frame and after switching the high pass filter to the second corner frequency.

9. The system of claim 1 wherein the high pass filter has a switchable corner frequency.

10. The system of claim 9 wherein the corner frequency of the high pass filter is switched from a higher corner frequency to a lower corner frequency during reception of a short preamble of a frame.

11. The system of claim 9 wherein the high pass filter is a negative feedback high pass filter with the feedback path opened during reception of a short preamble of a frame.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2010
From: WIONICS TECHNOLOGIES, INC. FORMERLY KNOWN AS WIONICS RESEARCH
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 024072/0640 →
CHANGE OF NAME Recorded Sep 13, 2005
From: ORION MICROELECTRONICS CORPORATION
To: WIONICS RESEARCH
Reel/Frame 016787/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2004
From: LI, KUANGYU; TANG, SONG-NIEN; CHENG, JACKIE K.; SOE, ZAW MIN
To: ORION MICROELECTRONICS CORPORATION
Reel/Frame 015061/0980 →
Continuity (1)
Related Publication 20050258989A1 · Nov 24, 2005