Flow control by supplying a remote start bit onto a single-wire bus
View Patent ↗A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.
1. A method comprising:
(a) writing remote data bits into a transmit memory buffer, wherein the remote data bits are transmitted with a remote start bit over a single-wire communication bus; and
(b) reading received data bits, wherein the received data bits are received from the single-wire communication bus, wherein the received data bits are preceded by the remote start bit, and wherein the receive data bits are supplied by a target device onto the single-wire communication bus before a subsequent remote start bit is detected on the single-wire communication bus by the target device.
2. A method comprising:
(a) writing remote data bits into a transmit memory buffer, wherein the remote data bits are transmitted with a remote start bit over a single-wire communication bus;
(b) reading received data bits, wherein the received data bits are received from the single-wire communication bus, and wherein the received data bits are preceded by the remote start bit; and
(c) writing subsequent remote data bits into the transmit memory buffer after (a) and before (b), wherein the subsequent remote data bits are transmitted with a subsequent remote start bit over the single-wire communication bus, wherein the subsequent remote start bit is received from the single-wire communication bus after the received data bits are received from the single-wire communication bus.
3. A method comprising:
(a) writing remote data bits into a transmit memory buffer, wherein the remote data bits are transmitted with a remote start bit over a single-wire communication bus; and
(b) reading received data bits, wherein the received data bits are received from the single-wire communication bus, wherein the received data bits are preceded by the remote start bit, wherein the received data bits are supplied by a target device onto the single-wire communication bus and are received by a host PC from the single-wire communication bus, and wherein the writing in (a) is performed by a driver for the target device that plugs into an operating system running on the host PC.
4. A device comprising:
a first-in-first-out transmit memory buffer;
a first-in-first-out receive memory buffer that has a number of free bytes; and
flow control logic circuitry that fills the first-in-first-out transmit memory buffer with a number of bytes of data that is less than or equal to the number of free bytes in the first-in-first-out receive memory buffer.
5. The device of claim 4 , wherein an operating system reads received data bits out of the first-in-first-out receive memory buffer freeing up the number of free bytes in the first-in-first-out receive memory buffer.
6. The device of claim 5 , wherein the operating system runs on a central processing unit, and wherein the operating system reads the received data bits out of the first-in-first-out receive memory buffer in response to an interrupt command to the central processing unit.
7. The device of claim 4 , wherein a central processing unit reads received data bits out of the first-in-first-out receive memory buffer, wherein the received data bits are received from a single-wire communication bus, and wherein the received data bits are preceded by a remote start bit.
8. The device of claim 4 , wherein the flow control logic circuitry fills the first-in-first-out transmit memory buffer with bytes of data comprising a hex character [FF].
9. The device of claim 4 , further comprising:
a single-wire communication bus coupled both to the first-in-first-out transmit memory buffer and to the first-in-first-out receive memory buffer.
10. The device of claim 9 , wherein the single-wire communication bus is coupled to the first-in-first-out transmit memory buffer through a transmit shift register.
11. The device of claim 9 , wherein the single-wire communication bus is coupled to an open-drain interface.
12. A system comprising:
a single-wire communication bus, wherein multiple receive data bits flow over the single-wire communication bus to a receiving device; and
means for controlling how the multiple receive data bits flow over the single-wire communication bus by supplying a single remote start bit onto the single-wire communication bus, wherein the means supplies the remote start bit onto the single-wire communication bus by supplying a hex character [FF] onto the single-wire communication bus.
13. The system of claim 12 , wherein an RS232 character comprises the remote start bit and the hex character [FF].
14. A method comprising:
(a) writing remote data bits into a transmit memory buffer, wherein the remote data bits are transmitted with a remote start bit over a single-wire communication bus;
(b) reading received data bits, wherein the received data bits are received from the single-wire communication bus, wherein the remote start bit occupies a pulse duration that immediately precedes the received data bits, and wherein a first RS232 character comprises the remote start bit and the received data bits; and
(c) receiving a second RS232 character, wherein the first RS232 character and the second RS232 character are received back-to-back without any inter-character pause.
15. The device of claim 4 , wherein sixty-four Kbytes of data are received into the first-in-first-out receive memory buffer after the device receives a single read request command.
16. The method of claim 1 , wherein the received data bits convey more than a single bit of data.
17. The method of claim 1 , wherein the remote start bit occupies a pulse duration that immediately precedes the received data bits.
18. The method of claim 1 , wherein an RS232 character comprises the remote start bit and the received data bits.
19. The method of claim 1 , wherein the remote start bit is a digital logic low, and each of the remote data bits is a digital logic high.
20. The method of claim 1 , wherein eight remote data bits are written in (a), and the remote data bits represent the hex character [FF].
21. The method of claim 1 , wherein the transmit memory buffer is a first-in-first-out memory buffer of a universal asynchronous receiver/transmitter.
22. The method of claim 1 , further comprising:
(c) writing additional remote data bits into the transmit memory buffer after reading the received data bits in (b).
23. The method of claim 1 , wherein the received data bits are supplied by a target device onto the single-wire communication bus and are received by a host PC from the single-wire communication bus, and wherein the writing in (a) is performed by an operating system running on the host PC.
24. The system of claim 12 , wherein data is both transmitted and received over the single-wire communication bus.
25. The system of claim 12 , wherein the means comprises an operating system.
26. The system of claim 12 , wherein the means comprises a universal asynchronous receiver/transmitter.
27. The system of claim 12 , wherein the single remote start bit occupies a pulse duration that immediately precedes the multiple receive data bits.