Semiconductor device and method for fabricating the same
View Patent ↗As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.
1. A method for fabricating a semiconductor device, comprising the steps of:
a) forming a gate insulating film over an active region of a substrate;
b) forming a silicon film over the gate insulating film;
c) patterning the silicon film, thereby forming a gate electrode;
d) performing ion implantation of an impurity using at least the gate electrode as a mask, thereby forming a source/drain region including a heavily doped impurity region;
e) performing first thermal treatment for activating the impurity introduced into the gate electrode; and
f) performing second thermal treatment for activating the impurity introduced into the gate electrode and the source/drain region at a higher temperature for a shorter time than the first thermal treatment is performed,
wherein the active region includes an NMISFET formation region and a PMISFET formation region,
wherein in the step c), a gate electrode of the NMISFET and a gate electrode of the PMISFET are formed,
wherein in the step d), an n-type impurity and a p-type impurity are separately ion-implanted into the NMISFET formation region and the PMISFET formation region, respectively,
wherein after the step b) and before the step c), an n-type impurity is ion-implanted into part of the silicon film located in the NMISFET formation region while introduction of an impurity is not performed to part of the silicon film located in the PMISFET formation region, and a p-type impurity is introduced into the gate electrode of the PMISFET.
2. The method of claim 1 , further comprising:
after the step c) and before the step d),
the step of performing ion implantation of an impurity at a low concentration using the gate electrode as a mask, thereby forming a lightly doped impurity region; and
the step of forming a sidewall covering a side surface of the gate electrode,
wherein in the step d), ion implantation of an impurity is performed at a high concentration using the gate electrode and the sidewall as masks, thereby forming a source/drain region including the lightly doped impurity region and the heavily doped impurity region.
3. The method of claim 1 ,
wherein in the step of e), the first thermal treatment is performed at a temperature higher than 550°C. and lower than 650° C. for a time equal to or longer than 10 seconds, and
wherein in the step f), the second thermal treatment is performed at a temperature higher than 1000° C. and lower than 1100° C. and for a time equal to or longer than 10 seconds.
4. The method of claim 3 , wherein in the step f), as the second thermal treatment, flash annealing or spike annealing is performed.
5. The method of claim 1 , wherein in the step b), a lower silicon film and an upper silicon film made of polysilicon and including at least a single layer is formed, thereby obtaining, before the step d), a lower gate electrode made of polysilicon having a large grain size and an upper gate electrode made of polysilicon having a smaller grain size than that of the lower gate electrode and including at least a single layer.
6. The method of claim 5 , wherein in the step b), an amorphous silicon film is formed as the lower silicon film.
7. The method of claim 5 , wherein the thickness of the lower silicon film formed in the step b) is larger than a dimension by which the heavily doped impurity region of the source/drain region is magnified due to the second thermal treatment and smaller than the thickness of the upper silicon film.
8. The method of claim 5 , wherein the thickness of the lower silicon film formed in the step b) is not less than 20 nm and not more than 50 nm.
9. A semiconductor device comprising:
a substrate;
a gate insulating film formed over an active region of the substrate:
a gate electrode formed over the gate insulating film and including a lower gate electrode made of polysilicon having a large gain size and an upper gate electrode having a smaller grain size than that of the lower electrode and including at least a single polysilicon layer; and
a source/drain region formed in each of respective regions of the active region located on both sides of the gate electrode and including a heavily doped impurity region,
wherein the thickness of the lower gate electrode is larger than a dimension by which the heavily doped impurity region of the source/drain region is magnified when thermal treatment for activating the impurity in the gate electrode is performed and smaller than the thickness of the upper gate electrode.
10. The semiconductor device of claim 9 ,
wherein the source/drain region is formed in a region of the active region located between the heavily doped impurity region and a region of the active region located directly under the gate electrode and includes a lightly doped impurity region containing an impurity at a lower concentration than that in the heavily doped impurity region, and
wherein the semiconductor device further includes a sidewall covering a side surface of the gate electrode.
11. The semiconductor device of claim 9 , wherein the thickness of the lower gate electrode is not less than 20 nm and not more than 50 nm.