Digitally programmable I/Q phase offset compensation
Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.
1. A frequency synthesizer circuit comprising:
a phase locked loop having a voltage controlled oscillator producing an output frequency;
a frequency divider receiving the output frequency of the voltage controlled oscillator and producing differential in-phase and quadrature signals; and
a phase offset compensation circuit for compensating a phase offset between the in-phase and quadrature signals, the phase offset compensation circuit comprising:
first pairs of series connected MOS varactors, each pair coupled between transmission lines of said in-phase differential signals;
a first group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said first pairs of MOS varactors;
second pairs of series connected MOS varactors, each pair coupled between transmission lines of said quadrature differential signals;
a second group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said second pairs of MOS varactors; and
a phase offset compensation logic circuit controlling the bias voltage controllers of the first and second groups in response to a phase offset compensation value received by the logic circuit to adjust the relative phases of the in-phase and quadrature signals.
2. The circuit claimed in claim 1 , wherein said MOS varactors are coupled between said transmission lines at their respective gates, and
wherein said respective bias voltages are applied to said bodies of said MOS varactors through source and drain regions of said MOS varactors.
3. The circuit claimed in claim 1 , wherein the sets of said first pairs of MOS varactors contain respective numbers of pairs of MOS varactors that increase in a binary fashion, and
wherein the sets of said second pairs of MOS varactors contain respective numbers of pairs of MOS varactors that increase in a binary fashion.
4. The circuit claimed in claim 1 , wherein said bias voltage controllers switch the bias voltages applied to the bodies of the MOS varactors between a first voltage producing a first capacitance and a second voltage producing a second capacitance that is higher than the first capacitance.
5. The circuit claimed in claim 4 , wherein said first voltage is a supply voltage and said second voltage is a ground voltage.
6. The circuit claimed in claim 4 , wherein said first voltage is a voltage that is higher than a supply voltage.
7. The circuit claimed in claim 4 , wherein said second voltage is a voltage that is lower than a ground voltage.
8. A circuit for modulating or demodulating a signal, comprising:
a frequency synthesizer circuit producing differential in-phase and quadrature signals;
a first mixer receiving the differential in-phase signals and first differential input signals and producing first differential output signals;
a second mixer receiving the differential quadrature signals and second differential input signals and producing second differential output signals; and
a phase offset compensation circuit for compensating a phase offset between the in-phase and quadrature signals, the phase offset compensation circuit comprising:
first pairs of series connected MOS varactors, each pair coupled between transmission lines of said in-phase differential signals;
a first group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said first pairs of MOS varactors;
second pairs of series connected MOS varactors, each pair coupled between transmission lines of said quadrature differential signals;
a second group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said second pairs of MOS varactors; and
a phase offset compensation logic circuit controlling the bias voltage controllers of the first and second groups in response to a phase offset compensation value received by the logic circuit to adjust the relative phases of the in-phase and quadrature signals.
9. The circuit claimed in claim 8 , wherein said MOS varactors are coupled between said differential signals at their respective gates, and
wherein said respective bias voltages are applied to said bodies of said MOS varactors through source and drain regions of said MOS varactors.
10. The circuit claimed in claim 8 , wherein the sets of said first pairs of MOS varactors contain numbers of pairs of MOS varactors that increase in a binary fashion, and
wherein the sets of said second pairs of MOS varactors contain numbers of pairs of MOS varactors that increase in a binary fashion.
11. The circuit claimed in claim 8 , wherein said bias voltage controllers switch the bias voltages applied to the bodies of the varactors between a first voltage producing a first capacitance and a second voltage producing a second capacitance that is higher than the first capacitance.
12. The circuit claimed in claim 11 , wherein said first voltage is a supply voltage and said second voltage is a ground voltage.
13. The circuit claimed in claim 11 , wherein said first voltage is a voltage that is higher than a supply voltage.
14. The circuit claimed in claim 11 , wherein said second voltage is a voltage that is lower than a ground voltage.
15. A phase offset compensation circuit for compensating a phase offset between first and second pairs of differential signals, comprising:
first pairs of series connected MOS varactors, each pair coupled between transmission lines of a first of said pairs of differential signals;
a first group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said first pairs of MOS varactors;
second pairs of series connected MOS varactors, each pair coupled between transmission lines of a second of said pairs of differential signals;
a second group of bias voltage controllers, each of said bias voltage controllers applying respective bias voltages to bodies of respective sets of said second pairs of MOS varactors; and
a phase offset compensation logic circuit controlling the bias voltage controllers of the first and second groups in response to a phase offset compensation value received by the logic circuit.
16. The circuit claimed in claim 15 , wherein the sets of said first pairs of MOS varactors contain respective numbers of pairs of MOS varactors that increase in a binary fashion, and
wherein the sets of said second pairs of MOS varactors contain respective numbers of pairs of MOS varactors that increase in a binary fashion.
17. The circuit claimed in claim 15 , wherein said bias voltage controllers switch the bias applied to the bodies of the varactors between a first voltage producing a first capacitance and a second voltage producing a second capacitance that is higher than the first capacitance.
18. The circuit claimed in claim 17 , wherein said first voltage is a supply voltage and said second voltage is a ground voltage.
19. The circuit claimed in claim 17 , wherein said first voltage is a voltage that is higher than a supply voltage.
20. The circuit claimed in claim 17 , wherein said second voltage is a voltage that is lower than a ground voltage.
21. The circuit claimed in claim 15 , wherein said MOS varactors are coupled between said transmission lines at their respective gates, and
wherein said respective bias voltages are applied to said bodies of said MOS varactors through source and drain regions of said MOS varactors.
22. A method for compensating phase offset between differential in-phase and quadrature signals of a frequency synthesizer, comprising:
measuring a phase offset between the differential in-phase and quadrature signals; and
selectively applying bias voltages to bodies of series connected MOS varactors coupled between the transmission lines of respective pairs of the differential in-phase signals and the differential quadrature signals to produce a delay in one of said pair of differential in-phase signals and said pair of differential quadrature signals to compensate said measured phase offset.
23. The method claimed in claim 22 , wherein said bias voltages are applied by bias voltage controllers under the control of a phase offset compensation logic circuit.
24. The method claimed in claim 22 , wherein said phase offset compensation logic circuit controls said bias voltage controllers in accordance with a binary phase offset compensation value received by the logic circuit representing a phase offset compensation to be produced.
25. The method claimed in claim 22 , wherein said method of compensating phase offset is performed at startup of a device incorporating the frequency synthesizer using a fixed compensation value determined in advance for the frequency synthesizer.