Current mode output stage circuit with open loop DC offset reduction
An output stage circuit for a current mode device provides open loop reduction or cancellation of DC offset in differential output signals. Differential input signals are received and sourcing current mirrors provide mirrors of the differential input signals to output nodes. Sinking current mirrors also provide mirrors of opposite polarity of the differential input signals to the output nodes corresponding to the opposing sourcing current mirrors. The summing of the mirror currents at the output nodes substantially reduces or eliminates the DC offset components present in the input signals.
1. An output stage for a current mode circuit, comprising:
a first reference transistor for receiving an input current I in comprised of a DC bias component I DC1 and a signal component I sig ;
a first sourcing current mirror for producing a mirror of the input current I in at a first output node;
a first sinking current mirror for producing a mirror of the input current I in at a second output node, the polarity of current produced by the first sinking current mirror being opposite to the polarity of current produced by the first sourcing current mirror;
a second reference transistor for receiving a complementary input current −I in comprised of a DC bias component I DC2 and a signal component −I sig ;
a second sourcing current mirror for producing a mirror of the complementary input current −I in at the second output node; and
a second sinking current mirror for producing a mirror of the complementary input current −I in at the first output node, the polarity of current produced by the second sinking current mirror being opposite to the polarity of current produced by the second sourcing current mirror.
2. The output stage claimed in claim 1 , wherein the first and second sourcing current mirrors and the first and second sinking current mirrors provide approximately equal gains.
3. The output stage claimed in claim 1 , wherein the first sinking current mirror comprises:
a first mirror transistor for producing a mirror of the input current I in in a third reference transistor; and
a second mirror transistor for producing a mirror of the current in the third reference transistor at the second output node, and
wherein the second sinking current mirror comprises:
a third mirror transistor for producing a mirror of the complementary input current −I in in a fourth reference transistor; and
a fourth mirror transistor for producing a mirror of the current in the fourth reference transistor at the first output node.
4. The output stage claimed in claim 3 , wherein the first reference transistor and the second reference transistor are matched transistors,
wherein the first sourcing current mirror, the second sourcing current mirror, the first mirror transistor and the third mirror transistor are matched transistors, and
wherein the third reference transistor, the fourth reference transistor, the second mirror transistor and the fourth mirror transistor are matched transistors.
5. The output stage claimed in claim 1 , wherein the first sourcing current mirror and the second sourcing current mirror comprise matched transistors.
6. The output stage claimed in claim 1 , wherein the first reference transistor and the second reference transistor are matched transistors.
7. The output stage claimed in claim 1 , further comprising respective transistors coupled between the first sourcing current mirror and the first output, between the second sourcing current mirror and the second output, between the first sinking current mirror and the second output, and between the second sinking current mirror and the first output, for receiving respective bias voltages at their gates to regulate output impedance of the output stage.
8. The output stage claimed in claim 1 , further comprising respective switches for switching the first and second sourcing current mirrors and the first and second sinking current mirrors into and out of the output stage.
9. The output stage claimed in claim 1 , further comprising:
a third sourcing current mirror for producing a mirror of the input current I in at the first output node;
a third sinking current mirror for producing a mirror of the input current I in at the second output node, the polarity of current produced by the third sinking current mirror being opposite to the polarity of current produced by the third sourcing current mirror;
a fourth sourcing current, mirror for producing a mirror of the complementary input current −I in at the second output node; and
a fourth sinking current mirror for producing a mirror of the complementary input current −I in at the first output node, the polarity of current produced by the fourth sinking current mirror being opposite to the polarity of current produced by the fourth sourcing current mirror.
10. The output stage claimed in claim 9 , further comprising:
respective switches for switching the first and second sourcing current mirrors and the first and second sinking current mirrors into and out of the output stage; and
respective switches for switching the third and fourth sourcing current mirrors and the third and fourth sinking current mirrors into and out of the output stage.
11. The output stage claimed in claim 10 , wherein the first and second sourcing current mirrors and the first and second sinking current mirrors produce output currents having a first ratio to the input currents, and
wherein the third and fourth sourcing current mirrors and the third and fourth sinking current mirrors produce output currents having a second ratio to the input currents.
12. The output stage claimed in claim 11 , wherein the first ratio is approximately equal to the second ratio.
13. The output stage claimed in claim 11 , wherein the first ratio is different than the second ratio.
14. A method for reducing DC bias in a differential signal pair, comprising:
receiving an input current I in and a complementary input current −I in , the input current I in being comprised of a DC bias component I DC1 and a signal component I sig , and the complementary input current −I in being comprised of a DC bias component I DC2 and a signal component −I sig ;
supplying a first mirror of the input current I in to a first output node;
supplying a second mirror of the input current I in to a second output node, the second mirror of the input current I in having a polarity with respect to the second output node that is opposite the polarity of the first mirror of the input current I in with respect to the first output node;
supplying a first mirror of the complementary input current −I in to the second output node, the first mirror of the complementary input current −I in having a polarity with respect to the second output node that is the same as the polarity of the second mirror of the input current I in with respect to the second output node; and
supplying a second mirror of the complementary input current −I in to the first output node, the second mirror of the complementary input current −I in having a polarity with respect to the first output node that is the same as the polarity of the first mirror of the input current I in with respect to the first output node.