IP Library Granted Patent US 7,701,323
Granted Patent B1
US 7,701,323 · App. 10/857,830 · Granted Apr 20, 2010

Low profile discrete electronic components and applications of same

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Quick Facts
Patent No.
US 7,701,323
App. No.
10/857,830
Granted
Apr 20, 2010
Kind
B1
Abstract

Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.

Claims (23)

1. A multi-layer electronic structure comprising:

first and second conductive layers disposed substantially parallel to one another;

a resistive layer disposed between the first and second conductive layers, the resistive layer having a first resistive circuit path that includes a first terminus and a second terminus,

a first insulating layer disposed between the resistive layer and the first conductive layer;

a second insulating layer disposed between the resistive layer and the second conductive layer;

a first through hole in the first insulating layer extending from the first conductive layer to the first terminus; and,

a second through hole in the second insulating layer extending from the second conductive layer to the second terminus; wherein a straight line extending from the first terminus to the second terminus is substantially parallel to the first conductive layer.

2. The multi-layer electronic structure of claim 1 wherein a separation distance between the first and second insulating layers is less than 500 μm.

3. The multi-layer electronic structure of claim 1 wherein a separation distance between the first and second insulating layers is less than 100 μm.

4. The multi-layer electronic structure of claim 1 wherein the first resistive circuit path follows a geometrically non-linear path between the first terminus and the second terminus.

5. The multi-layer electronic structure of claim 4 wherein the geometrically non-linear path comprises at least one sharp angle.

6. The multi-layer electronic structure of claim 5 wherein the at least one sharp angle comprises at least one right angle.

7. The multi-layer electronic structure of claim 5 wherein the first resistive circuit path includes at least one segment that is not parallel to the first conductive layer.

8. The multi-layer electronic structure of claim 1 , wherein the shape of the discrete electronic device is either a cylinder or a polyhedron in shape, the shape having a height measured from the first conductive layer to the second conductive layer, and wherein a polyhedron shape further has width defined by a linear distance across the first conductive layer.

9. The multi-layer electronic structure of claim 8 , wherein the height is less than the width.

10. The multi-layer electronic structure of claim 1 wherein the multi-layer electrical structure comprises a printed circuit.

11. The multi-layer electronic structure of claim 1 wherein the multi-layer electrical structure comprises an IC package.

12. The multi-layer electronic structure of claim 1 , the resistive layer further comprising a second resistive circuit path.

13. The multi-layer electronic structure of claim 1 wherein at least portion of the first resistive circuit path is substantially parallel to the first conductive layer.

14. The multi-layer electronic structure of claim 1 wherein the first resistive circuit path follows a geometrically linear path between the first terminus and the second terminus.

15. The multi-layer electronic structure of claim 1 wherein the first insulating layer abuts a surface of the resistive layer.

16. The multi-layer electronic structure of claim 15 wherein the second insulating layer abuts a surface of the resistive layer.

17. The multi-layer electronic structure of claim 1 , wherein an interior surface of the first through hole comprises a conductive coating.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0596 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: INTERCONNECT PORTFOLIO, LLC; INTELLASYS BEC LIMITED; TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0634 →
LICENSE Recorded Mar 4, 2009
From: INTERCONNECT PORTFOLIO LLC
To: TECHNOLOGY PROPERTIES LIMITED LLC
Reel/Frame 022343/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2008
From: NOVIAS LLC
To: INTERCONNECT PORTFOLIO, LLC
Reel/Frame 021861/0127 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2008
From: HOLDERS, SECURE NOTE; ANDERSON, DAN; FJELSTAD, JOE; GRUNDY, KEVIN; GRUNDY, LAWRENCE; STEPOVICH, MATT
To: NOVIAS, LLC
Reel/Frame 021744/0512 →
FORECLOSURE BY SECURE NOTE HOLDERS Recorded Aug 7, 2008
From: SILICON PIPE, INC.
To: SECURE NOTE HOLDERS: DAN ANDERSON, JOSEPH FJELSTAD, KEVIN GRUNDY, LAURANCE GRUNDY, MATT STEPOVICH
Reel/Frame 021380/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2004
From: FJELSTED, JOSEPH C.; GRUNDY, KEVIN P.; SEGARAM, PARA K.; WEIDEMANN, WILLIAM F.; OBENHUBER, INESSA (EXECUTOR TO THE ESTATE OF THOMAS J. OBENHUBER
To: SILICON PIPE, INC.
Reel/Frame 015198/0923 →