Reset circuitry for an integrated circuit
View Patent ↗Reset circuitry for an integrated circuit is presented. An internal oscillator produces an oscillating signal upon power-up of the integrated circuit. The internal oscillator is not dependent on signals generated outside the integrated circuit. An electro-static discharge blocker circuit receives an external reset signal generated outside the integrated circuit. The electrostatic discharge blocker circuit utilizes the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset signal.
1. Reset circuitry for an integrated circuit comprising:
an internal oscillator that produces an oscillating signal upon power-up of the integrated circuit, the internal oscillator not being dependent on signals generated outside the integrated circuit;
an electro-static discharge blocker circuit, the electro-static discharge blocker circuit receiving an external reset signal generated outside the integrated circuit, the electro-static discharge blocker circuit utilizing the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset signal; and
a synchronizer that synchronizes de-assertion of the internal reset signal, the synchronizer utilizing a system clock generated external to the integrated circuit when performing synchronization.
2. Reset circuit as in claim 1 wherein the internal oscillator is a ring oscillator.
3. Reset circuit as in claim 1 wherein the internal oscillator is a ring oscillator that includes a counter.
4. Reset circuitry as in claim 1 wherein the electro-static discharge blocker comprises:
a plurality of flip-flops connected in series; and,
circuitry that performs a logic OR operation on outputs of the plurality of flip-flops.
5. Reset circuitry as in claim 1 ,
wherein the internal reset signal is used to reset flip-flops within the synchronizer, allowing the internal reset signal to bypass the synchronizer without requiring the system clock to be functional.
6. Reset circuitry as in claim 1 ,
a plurality of flip-flops, the internal reset signal being coupled to a reset input of each of the plurality of flip-flops, thereby allowing the internal reset signal to bypass the synchronizer without requiring the system clock to be functional.
7. Reset circuitry as in claim 6 , wherein:
the internal oscillator comprises a ring oscillator; and,
the electro-static discharge blocker circuit comprises:
a second plurality of flip-flops connected in series, and
a logic OR gate that performs a logic AND operation on outputs of the second plurality of flip-flops.
8. Reset circuitry for an integrated circuit comprising:
oscillating means for producing an oscillating signal upon power-up of the integrated circuit, the producing of the oscillating signal not being dependent on signals generated outside the integrated circuit;
blocking means for receiving an external reset signal generated outside the integrated circuit and utilizing the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset and
synchronizing means for synchronizing de-assertion of the internal reset signal utilizing a system clock generated external to the integrated circuit.
9. Reset circuit as in claim 8 wherein the oscillating means comprises a ring oscillator.
10. Reset circuit as in claim 8 wherein the oscillating means comprises a ring oscillator that includes a counter.
11. Reset circuitry as in claim 8 wherein the blocking means comprises:
a plurality of flip-flops connected in series; and,
a circuitry that performs a logic OR operation on outputs of the plurality of flip-flops.
12. Reset circuitry as in claim 8 , wherein the synchronizing means comprises:
a plurality of flip-flops, the internal reset signal being coupled to a reset input to each of the plurality of flip-flops, thereby allowing the internal reset signal to propagate through the integrated circuit within the system clock being functional.
13. Reset circuitry as in claim 12 , wherein:
the oscillating means comprises a ring oscillator; and,
the blocking means comprises:
a second plurality of flip-flops connected in series, and
circuitry that performs a logic OR operation on outputs of the second plurality of flip-flops.
14. A method for performing resets within an integrated circuit comprising:
producing an oscillating signal upon power-up of the integrated circuit, the producing of the oscillating signal not being dependent on signals generated outside the integrated circuit;
receiving an external reset signal generated outside the integrated circuit and utilizing the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset signal; and,
synchronizing de-assertion of the internal reset signal utilizing a system clock generated external to the integrated circuit.
15. A method as in claim 14 wherein producing an oscillating signal is performed using a ring oscillator.
16. A method as in claim 14 wherein producing an oscillating signal is performed using a ring oscillator that includes a counter.
17. Method as in claim 14 , additionally comprising:
coupling the internal reset signal to a reset input to each of a plurality of flip-flops used in synchronizing de-assertion of the internal reset, thereby allowing the internal reset signal to propagate through the integrated circuit without the system clock being functional.