Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same

1. A method of fabricating an integrated circuit semiconductor device, the method comprising:

forming a first buried insulating layer and a second buried insulating layer in a first trench in a cell region and an alignment key region trench of an alignment key region, respectively, of a silicon substrate;

forming a first insulating pattern and a second insulating pattern in the cell region and an overlay key region, respectively, of the silicon substrate;

covering the cell region with a first photoresist pattern;

forming a second trench and a third trench by etching the silicon substrate in the overlay key region and the alignment key region, respectively, by using the first photoresist pattern, the second insulating pattern and the second buried insulating layer as a mask;

forming a conductive layer over the entire surface of the silicon substrate including the cell region, the overlay key region, and the alignment key region;

forming a second photoresist pattern over the conductive layer by using the third trench formed in the alignment key region as an alignment key and using the second insulating pattern as an overlay key; and

forming a conductive pattern by patterning the conductive layer using the second photoresist pattern as a mask, the conductive pattern formed by correcting overlay and alignment errors using the second insulating pattern.

2. The method of claim 1 , wherein each of the first insulating pattern and the second insulating pattern is formed of a material selected from a group consisting of SiO 2 , SiON, Si 3 N 4 and any combination thereof.

3. The method of claim 1 , wherein each of the first insulating pattern and the second insulating pattern is formed of a triple layer of SiO 2 , Si 3 N 4 , and SiO 2 .

4. The method of claim 1 , wherein each of the first insulating pattern and the second insulating pattern is formed to a thickness of about 100 Å to about 300 Å.

5. The method of claim 1 , wherein each of the first conductive pattern, the second conductive pattern, and the third conductive pattern is formed of a doped polysilicon layer.

6. The method of claim 1 , wherein the silicon substrate in the overlay key region and the alignment key region is plasma etched using a gas selected from a group consisting of Cl 2 gas, HBr gas, and BCl 3 gas.

7. A method of fabricating an integrated circuit semiconductor device, the method comprising:

forming a first buried insulating layer and a second buried insulating layer in a first trench in a cell region and an alignment key region trench in an alignment key region, respectively, of a silicon substrate;

forming a first insulating pattern and a second insulating pattern in the cell region and an overlay key region, respectively, of the silicon substrate;

covering the cell region and the alignment key region with a first photoresist pattern;

forming a second trench by etching the silicon substrate in the overlay key region by using the first photoresist pattern and the second insulating pattern as a mask;

forming a conductive layer over the entire surface of the silicon substrate including the cell region, the overlay key region, and the alignment key region;

forming a second photoresist pattern over the conductive layer by using the alignment key region trench formed in the alignment key region as an alignment key and using the second insulating pattern as an overlay key; and

forming a conductive pattern by patterning the conductive layer using the second photoresist pattern as a mask, the conductive pattern formed by correcting overlay and alignment errors using the second insulating pattern.

8. The method of claim 7 , wherein each of the first insulating pattern and the second insulating pattern is formed of a material selected from a group consisting of SiO 2 , SiON, Si 3 N 4 and any combination thereof.

9. The method of claim 7 , wherein each of the first insulating pattern and the second insulating pattern is formed to a thickness of about 100 Å to about 300 Å.

10. The method of claim 7 , wherein each of the first conductive pattern, the second conductive pattern, and the third conductive pattern is formed of a doped polysilicon layer.

11. The method of claim 7 , wherein the silicon substrate in the overlay key region is plasma etched using a gas selected from a group consisting of Cl 2 gas, HBr gas, and BCl 3 gas.

12. A method of fabricating an integrated circuit semiconductor device comprising:

forming at least one trench in a semiconductor substrate, wherein the at least one trench is formed in an overlay key region of the semiconductor substrate;

forming an insulating pattern over the semiconductor substrate;

forming a conductive layer over the insulating pattern;

forming a photoresist pattern over the conductive layer using a step difference between the trench and the insulating pattern so that the insulating pattern functions as an overlay key; and etching the conductive layer using the photoresist pattern as a mask.

13. The method of claim 12 , further comprising:

forming at least one other trench in an alignment key region of the semiconductor substrate, the photoresist pattern being formed over the conductive layer using the at least one other trench as an alignment key.