Granted Patent B2

US 7,215,580 · App. 10/867,800 · Granted May 8, 2007

Abstract

Claims (10)

1. A method for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays, within the non-volatile memory, from a plurality of available arrays accessed at one time, the method comprising:

implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays;

before accessing any array, checking the number of currently active arrays against an allowed limit; and

waiting for the at least one of the arrays to complete before initiating the transfer to and from a further array,

thereby controlling flash memory accesses in a memory system configured to use concurrent operation in different flash memory arrays and allowing performance to be changed easily in systems supporting concurrent flash operations in different Flash arrays.

2. A non-volatile memory system which presents the logical characteristics of a disk storage device to a host system comprising:

a non-volatile memory incorporating a plurality of memory arrays; and

a controller including,

means for implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays; and

means for limiting the number of active arrays operating at one time, before accessing any array, checking the number of currently active arrays against an allowed limit, thereby controlling flash memory accesses in a memory system configured to use concurrent operation in different flash memory arrays and allowing performance to be changed easily in systems supporting concurrent flash operations in different Flash arrays.

Assignments (8)