IP Library Patent Application 10868129
Patent Application
App. No. 10/868,129

Systems and methods for managing distributed design chains

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Quick Facts
Patent No.
US None
App. No.
10/868,129
Abstract

Systems, architectures, and data structures are described which are used to manage distributed design chains, specifically for domains in which data reside in multiple applications and are linked through complex interrelationships. The design chains or design networks integrated by the invention may include multiple companies in multiple sites collaborating to design and develop a new product. The invention is intended to integrate seamlessly and transparently with existing, diverse legacy applications, which include inter-linked data relevant to the design, thereby addressing the needs identified above.

Claims (8)

1 . A method of monitoring a design of a product, wherein the design is at least partially encoded in one or more electronic files, the method comprising:

receiving meta-data regarding the design from the one or more electronic files, the meta-data including one or more design goals for the design and one or more schedules for the design;

generating a user interface from the meta-data, the user interface including one or more graphs indicating one or more of the group consisting of a measurement of a current status of the design against one or more of the design goals and a measurement of the current status of the design against the one or more schedules for the design.

2 . The method of claim 1 , wherein the product includes an integrated circuit.

3 . The method of claim 2 , wherein the one or more design goals include a metric for a space occupied by the integrated circuit.

4 . The method of claim 2 , wherein the one or more design goals include a metric for power consumed by the integrated circuit.

5 . The method of claim 2 , wherein the one or more design goals include a metric for a timing of the integrated circuit.

6 . The method of claim 2 , wherein the one or more design goals include a metric for verification of a logic of the integrated circuit.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Aug 4, 2017
From: SILICON VALLEY BANK
To: COLLABNET, INC.
Reel/Frame 043194/0905 →
RELEASE OF SECURITY INTEREST Recorded Aug 3, 2017
From: SILICON VALLEY BANK
To: COLLABNET, INC.
Reel/Frame 043192/0399 →
RELEASE OF SECURITY INTEREST Recorded Jul 7, 2017
From: LEADER VENTURES, LLC
To: COLLABNET, INC.
Reel/Frame 042931/0453 →
SECURITY AGREEMENT Recorded Oct 28, 2014
From: COLLABNET HOLDINGS, INC.; COLLABNET, INC.
To: SILICON VALLEY BANK
Reel/Frame 034069/0460 →
SECURITY AGREEMENT Recorded Jul 20, 2010
From: COLLABNET, INC.
To: LEADER VENTURES, LLC, AS AGENT
Reel/Frame 024716/0478 →
SECURITY AGREEMENT Recorded Aug 31, 2009
From: COLLABNET, INC.
To: LEADER VENTURES, LLC
Reel/Frame 023172/0370 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2004
From: KRISHNAMURTHY, RAVI
To: COLLABNET, INC.
Reel/Frame 015397/0607 →