Optical add/drop interconnect bus for multiprocessor architecture

1. An apparatus, comprising:

an optical bus to interconnect processors of a multiprocessor system;

at least one electrical-to-optical (“E-O”) transmitter coupled to receive electrical signals from one of the processors and to convert the electrical signals to first optical signals to be guided onto the optical bus;

optical-to-electrical (“O-E”) receivers coupled to receive second optical signals from the optical bus and to convert the second optical signals to electrical signals for the processors; and

first optical couplers coupling the at least one E-O transmitter and the O-E receivers to the optical bus, wherein the at least one E-O transmitter comprises:

an input port to receive a continuous wave (“CW”) optical input;

an optical splitter to split the CW optical input into a first portion and a second portion;

a modulator to modulate the electrical signals onto the first portion of the CW optical input; and

an output port to output the second portion of the CW optical input to a next E-O transmitter of a next processor.

2. The apparatus of claim 1 , further comprising a circuit board to receive the processors thereon.

3. The apparatus of claim 2 , wherein the optical bus comprises one of an optical fiber and a planar waveguide.

4. The apparatus of claim 2 , further comprising:

a memory controller mounted to the circuit board to electrically couple to shared memory; and

a second optical coupler to optically couple the memory controller to the optical bus, the memory controller to provide the processors access to the shared memory through the optical bus.

5. The apparatus of claim 2 , further comprising:

an input/output (“I/O”) controller mounted to the circuit board to electrically couple to electrical I/O devices; and

a second optical coupler to optically couple the I/O controller to the optical bus, the I/O controller to provide the processors access to the electrical I/O devices through the optical bus.

6. The apparatus of claim 2 , further comprising the processors and wherein at least one E-O transmitter, at least one O-E receiver, and at least one processor are integrated into a single chip package mounted on the circuit board.

7. The apparatus of claim 2 , further comprising the processors and wherein at least one E-O transmitter, at least one O-E receiver, and at least one processor are integrated into a single semiconductor die.

8. The apparatus of claim 1 , wherein the first optical couplers comprise evanescent optical couplers.

9. The apparatus of claim 8 , wherein the evanescent optical couplers comprise bi-directional optical couplers to propagate the first optical signals in multiple directions on the optical bus and to receive the second optical signal from multiple directions on the optical bus.

10. The apparatus of claim 1 , further comprising multiple E-O transmitters to receive the electrical signals from the processors and optically coupled to the optical bus to convert the electrical signals to the first optical signals to be guided onto the optical bus.

11. The apparatus of claim 10 , further comprising an arbitration circuit to arbitrate write access to the optical bus between the processors.

12. The apparatus of claim 1 , further comprising:

multiple optical buses to interconnect the processors; and

multiple E-O transmitters, each of the multiple optical buses optically coupled to one of the multiple E-O transmitters, each of the multiple E-O transmitters to electrically couple to one of the processors,

wherein each of the multiple optical buses is optically coupled to multiple of the O-E receivers and wherein each processor is to electrically couple to multiple of the O-E receivers.

13. The apparatus of claim 1 , further comprising:

an optical source to generate a continuous wave (“CW”) optical signal; and

an optical distribution network to distribute portions of the CW optical signal to multiple E-O transmitters.