IP Library Granted Patent US 7,002,940
Granted Patent B2
US 7,002,940 · App. 10/868,948 · Granted Feb 21, 2006

Multiple-stage filtering device and method

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Quick Facts
Patent No.
US 7,002,940
App. No.
10/868,948
Granted
Feb 21, 2006
Kind
B2
Abstract

A filter is provided that is formed of multiple filter stages arranged in series. Each of these filter stages has an input tap at its input that can be selectively connected to a filter input signal, and an output tap at its and output that can be selectively connected to an output selection circuit. Adjacent pairs of filter stages can also be isolated from each other. By selectively connecting the various input and output taps, and selectively isolating pairs of filter stages from each other, the filter can be formed into a single long filter or a plurality of parallel filters anywhere in size from one filter stage up to half the total number of filter stages. The output selection circuit can then sequentially select whatever filter stage outputs are connected to it and provide those as a general filter output.

Claims (51)

1. A multiple-stage filtering circuit, comprising:

first through N th filter stages, formed in series, having first through N th input lines and first through N th output lines, respectively, each of the first through N th filter stages being configured to perform a filtering function;

an output circuit configured to provide a filter output signal;

input selection circuitry configured to selectively connect a filter input signal to any of the first through N th input lines;

output selection circuitry configured to selectively connect any of the first through N th output lines to the output circuit; and

filter stage isolation circuitry configured to selectively isolate any adjacent pair of the first through N th filter stages,

wherein N is an integer greater than one.

2. A multiple-stage filtering circuit, as recited in claim 1 , wherein the output circuit is a parallel data bus.

3. A multiple-stage filtering circuit, as recited in claim 1 , wherein the output circuit is an N-input, single output switch.

4. A multiple-stage filtering circuit, as recited in claim 1 , wherein N is evenly divisible by 6.

5. A multiple-stage filtering circuit, as recited in claim 1 , wherein the multiple-stage filtering circuit is implemented in an integrated circuit.

6. A multiple-stage filtering circuit, as recited in claim 1 , wherein the multiple-stage filtering circuit is implemented in an ultrawide bandwidth device.

7. A multiple-stage filtering circuit, as recited in claim 1 , wherein the input selection circuitry comprises a plurality of switches connected between the second through N th input lines and the filter input signal.

8. A multiple-stage filtering circuit, as recited in claim 1 , wherein the output selection circuitry comprises a plurality of switches connected between the first through (N−1) th output lines and the output selection circuitry.

9. A multiple-stage filtering circuit, as recited in claim 1 , wherein the filter isolation circuitry comprises a plurality of switches connected between pairs of the first through N th filter stages.

10. A multiple-stage filtering circuit, as recited in claim 1 , wherein the first input line of the first filter stage is directly connected to the filter input signal.

11. A multiple-stage filtering circuit, as recited in claim 1 , wherein the N th output line of the N th filter stage is directly connected to the output circuit.

12. A method of configuring a filter having N filter stages, comprising:

configuring the N-stage filter during a first transmission environment into J 1 first parallel sub-filters, each first parallel sub-filter comprising K 1 consecutive filter stages from the N-stage filter;

configuring the N-stage filter during a second transmission environment into J 2 second parallel sub-filters, each second parallel sub-filter comprising K 2 consecutive filter stages from the N-stage filter;

wherein J 1 , J 2 , K 1 , and K 2 are integers that each vary from 1 to N,

wherein J 1 >J 2 and K 1 <K 2 , and

wherein (J 1 ×K 1 )≦N and (J 2 ×K 2 )≦N.

13. A method of configuring a filter having N filter stages, as recited in claim 12 ,

wherein the first transmission environment has a first maximum effective range longer than a second maximum effective range for the second transmission environment, and

wherein the first transmission environment has a first maximum effective transmission speed slower than a second maximum effective transmission speed of the second transmission environment.

14. A method of configuring a filter having N filter stages, as recited in claim 12 , further comprising:

configuring the N-stage filter during a third transmission environment into J 3 third parallel sub-filters, each third parallel sub-filter comprising K 3 consecutive filter stages from the N-stage filter,

wherein J 3 and K 3 are each integers that each vary from 1 to N,

wherein J 1 ≧J 3 >J 2 , and K 1 <K 3 ≦K 2 , and

wherein (J 3 ×K 3 )≦N.

15. A method of configuring a filter having N filter stages, as recited in claim 14 ,

wherein the third transmission environment has a third maximum effective range shorter than the first maximum effective range for the first transmission environment, but longer than the second maximum effective range for the second transmission environment, and

wherein the third first transmission environment has a third maximum effective transmission speed faster than the first maximum effective transmission speed of the first transmission environment, but slower than the second maximum effective transmission speed of the second transmission environment.

16. A method of configuring a filter having N filter stages, as recited in claim 12 , further comprising:

configuring the N-stage filter during a third transmission environment into J 3 third parallel sub-filters, each third parallel sub-filter comprising K 3 consecutive filter stages from the N-stage filter,

wherein J 3 and K 3 are integers that each vary from 1 to N,

wherein J 1 >J 3 ≧J 2 , and K 1 ≦K 3 <K 2 , and

wherein (J 3 ×K 3 )≦N.

17. A method of configuring a filter having N filter stages, as recited in claim 16 ,

wherein the third transmission environment has a third maximum effective range shorter than the first maximum effective range for the first transmission environment, but longer than the second maximum effective range for the second transmission environment, and

wherein the third first transmission environment has a third maximum effective transmission speed faster than the first maximum effective transmission speed of the first transmission environment, but slower than the second maximum effective transmission speed of the second transmission environment.

18. A method of configuring a filter having N filter stages, as recited in claim 12 , wherein N is evenly divisible by 6.

19. A method of configuring a filter having N filter stages, as recited in claim 12 , further comprising

providing first output signals from the J 1 first parallel sub-filters to a switch during a first transmission environment; and

providing second output signals from the J 2 second parallel sub-filters to the switch during a second transmission environment.

20. A method of configuring a filter having N filter stages, as recited in claim 12 , further comprising

providing first output signals from the J 1 first parallel sub-filters to a data bus during a first transmission environment; and

providing second output signals from the J 2 second parallel sub-filters to the data bus during a second transmission environment.

21. A method of configuring a filter having N filter stages, as recited in claim 12 , wherein the method is implemented in an integrated circuit.

22. A method of configuring a filter having N filter stages, as recited in claim 12 , wherein the method is implemented in an ultrawide bandwidth device.

Assignments (29)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2005
From: MOTOROLA, INC.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015735/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2004
From: WELLBORN, MATTHEW L.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 015492/0717 →