Multiple match detection logic and gates for content addressable memory (CAM) devices
View Patent ↗Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including log 2 N stages of 2-to-1 multiple match gates, where N=2 k and k is a positive integer. The final MMF is set to an active level whenever at least two of the input match signals indicate a match condition and the AMF is set to an active level whenever at least one of the input match signals indicates a match condition.
1. A multiple match gate, comprising:
a first pull-down path defined by a first NMOS transistor having a gate terminal that is configured to receive a not any match signal NAM0 and a second NMOS transistor having a gate terminal that is configured to receive a not multiple match signal NMM1;
a second pull-down path defined by third NMOS transistor having a gate terminal that is configured to receive a not any match signal NAM1 and a fourth NMOS transistor having a gate terminal that is configured to receive a not multiple match signal NMM0;
a first pull-up path defined by a first PMOS transistor having a gate terminal that is configured to receive the not multiple match signal NMM0;
a second pull-up path defined by a second PMOS transistor having a gate terminal that is configured to receive the not multiple match signal NMM1;
a third pull-up path defined by a third PMOS transistor having a gate terminal that is configured to receive the not any match signal NAM0 and a fourth PMOS transistor having a gate terminal that is configured to receive the not any match signal NAM1; and
a multiple match flag (MMF) terminal that is electrically connected to said first and second pull-down paths and said first, second and third pull-up paths so that the following boolean expression is satisfied:
MMF=NOT (( NMM 0 ×NAM 1)+( NAM 0 ×NMM 1)).
2. The multiple match gate of claim 1 , further comprising:
a NAND gate that is configured to generate an any match flag (AMF) in response to the not any match signals NAM0 and NAM1.
3. A multiple match gate, comprising:
a first pull-up path defined by a first PMOS transistor having a gate terminal that is configured to receive an any match signal AM0 and a second PMOS transistor having a gate terminal that is configured to receive a multiple match signal MM1;
a second pull-up path defined by third PMOS transistor having a gate terminal that is configured to receive an any match signal AM1 and a fourth PMOS transistor having a gate terminal that is configured to receive a multiple match signal MM0;
a first pull-down path defined by a first NMOS transistor having a gate terminal that is configured to receive the multiple match signal MM0;
a second pull-down path defined by a second NMOS transistor having a gate terminal that is configured to receive the multiple match signal MM1;
a third pull-down path defined by a third NMOS transistor having a gate terminal that is configured to receive the any match signal AM0 and a fourth NMOS transistor having a gate terminal that is configured to receive the any match signal AM1; and
a not multiple match flag (NMMF) terminal that is electrically connected to said first and second pull-up paths and said first, second and third pull-down paths so that the following boolean expression is satisfied:
NMMF=NOT (( MM 0 +AM 1)×( AM 0 +MM 1)).
4. The multiple match gate of claim 3 , further comprising:
a NOR gate that is configured to generate a not any match flag (AMF) in response to the any match signals AM0 and AM1.