Soft-decision decoding using selective bit flipping
View Patent ↗A method or apparatus that can form and test a data block variant by flipping a selected potentially bad bit that is consecutive with 1 or 2 sequences of several potentially good bits of a received block. The variant correctability test is optionally repeated several times before receiving another data block, in the event of ECC failures, each repetition using a different block variant.
1. A method, comprising:
receiving a data block having a plurality of bits, the data block having one or more incorrect bits;
selecting one or more unreliable bits of the plurality of bits that are each consecutive with at least one sequence of a predetermined number of reliable bits;
forming a data block variant of the data block by flipping at least one of the selected unreliable bits; and
determining whether the data block variant is correctable.
2. The method as in claim 1 , further comprising:
correcting the data block variant in response to its being correctable.
3. The method as in claim 1 , further comprising:
repeating the selecting, forming, and determining for a plurality repetitions on the data block, each repetition resulting in a different data block variant.
4. The method as in claim 1 , further comprising:
receiving a second data block, each of the received data blocks being an estimate of one original data block; and
performing the selecting, forming, and determining on the second data block.
5. The method as in claim 1 , further comprising:
selecting the one or more unreliable bits so that each is situated in a respective N-bit symbol containing N−1 other bits that are reliable bits.
6. The method as in claim 1 , further comprising:
selecting the one or more unreliable bits so that each is situated in a symbol that meets at least one criterion of mutual isolation from other symbols with unreliable bits.
7. The method as in claim 1 , wherein the data block variant comprises at least one erased symbol, the at least one erased symbol not containing any flipped bits.
8. The method as in claim 1 , further comprising:
selecting at least one symbol of the received data block that has a located unreliable bit; and
erasing the at least one symbol so as to exclude the located unreliable bit from the received data block.
9. The method as in claim 1 , further comprising:
obtaining a scalar evaluation of each of the plurality of reliable bits; and
deriving the unreliable bit from an arithmetic combination of at least some of the scalar evaluations.
10. The method as in claim 1 , further comprising:
storing an original data block in a storage medium subject to degradation; and
receiving the received data block from an original data block that has degraded.
11. The method as in claim 1 , wherein the at least one sequence of a predetermined number of reliable bits succeeds each unreliable bit.
12. The method as in claim 1 , wherein the at least one sequence of a predetermined number of reliable bits proceeds each unreliable bit.
13. The method as in claim 1 , wherein selecting further comprises:
selecting one or more unreliable bits of the plurality of bits that are each between two sequences of a predetermined number of reliable bits.
14. The method as in claim 1 , further comprising:
determining whether bits are reliable and unreliable based on soft information.
15. The method as in claim 14 , further comprising:
utilizing a threshold of the soft information to determine whether bits are reliable and unreliable; and
changing the threshold to obtain a configured number of unreliable bits.
16. The method as in claim 1 , wherein the selected one or more unreliable bits of the plurality of bits are each consecutive with at least one sequence of a predetermined number of reliable bits of a symbol that is consecutive with a plurality of symbols having all reliable bits.
17. The method as in claim 1 , further comprising:
flipping a plurality of the selected unreliable bits to form the data block variant.
18. An apparatus, comprising:
a detector configured to receive a data block having a plurality of bits, the data block having one or more incorrect bits; and
error correction code (ECC) circuitry configured to i) select one or more unreliable bits of the plurality of bits that are each consecutive with at least one sequence of a predetermined number of reliable bits; ii) form a data block variant of the data block by flipping at least one of the selected unreliable bits; and iii) determine whether the data block variant is correctable.
19. The apparatus as in claim 18 , wherein the EEC circuitry is further configured to correct the data block variant in response to its being correctable.
20. The apparatus as in claim 18 , further comprising:
a storage medium configured to store the data block, wherein the storage medium is vulnerable to degradation.
21. The apparatus as in claim 18 , further comprising:
a data channel configured to transmit the data block to the detector, wherein the data channel is vulnerable to degradation.
22. The apparatus as in claim 18 , wherein the ECC circuitry is further configured to select the one or more unreliable bits so that each is situated in a respective N-bit symbol containing N−1 other bits that are reliable bits.
23. The apparatus as in claim 18 , wherein the ECC circuitry is further configured to select the one or more unreliable bits so that each is situated in a symbol that meets at least one criterion of mutual isolation from other symbols with unreliable bits.
24. The apparatus as in claim 18 , wherein the data block variant comprises at least one erased symbol, the at least one erased symbol not containing any flipped bits.
25. The apparatus as in claim 18 , wherein the ECC circuitry is further configured to:
select at least one symbol of the received data block that has a located unreliable bit; and
erase the at least one symbol so as to exclude the located unreliable bit from the received data block.
26. The apparatus as in claim 18 , wherein the ECC circuitry is further configured to select one or more unreliable bits of the plurality of bits that are each between two sequences of a predetermined number of reliable bits.
27. The apparatus as in claim 18 , wherein the detector is further configured to produce soft information for each bit of the received data block, and wherein the ECC circuitry is further configured to determine whether bits are reliable and unreliable based on soft information.
28. The apparatus as in claim 18 , wherein the ECC circuitry is further configured to flip a plurality of the selected unreliable bits to form the data block variant.
29. An apparatus, comprising:
means for receiving a data block having a plurality of bits, the data block having one or more incorrect bits;
means for selecting one or more unreliable bits of the plurality of bits that are each consecutive with at least one sequence of a predetermined number of reliable bits;
means for forming a data block variant of the data block by flipping at least one of the selected unreliable bits; and
means for determining whether the data block variant is correctable.