Delay-locked loop and a method of testing a delay-locked loop
View Patent ↗A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the dock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.
1. A delay-locked loop (DLL) of an integrated circuit (IC) comprising:
a selector having a reference clock input, a test clock input and an output, the selector being configured to select between the reference clock input and the test clock input and to provide the selected input on the selector output, a reference clock being delivered to the reference clock input and a test clock being delivered to the test clock input, the test clock being generated external to the IC;
a phase comparator having a first input and a second input, the first input of the phase comparator receiving the selector output, the second input of the phase comparator receiving a feedback clock, wherein when the reference clock input of the selector is selected, the phase comparator compares a phase of the feedback clock with a phase of the reference clock to determine a phase difference between the phase of the reference clock and the phase of the feedback clock, and wherein when the test clock input of the selector is selected, the phase comparator compares a phase of the test clock with the phase of the feedback clock to determine a phase difference between the phase of the test clock and the phase of the reference clock; and
a variable delay element, the variable delay element receiving the reference clock and the phase difference determined by the phase comparator as inputs, the variable delay element delays the reference clock by an amount that depends on the determined phase difference.
2. The DLL of claim 1 , wherein the feedback clock corresponds to an output of a clock buffer tree of the IC.
3. The DLL of claim 1 , wherein the test clock input of the selector is coupled to an input/output (I/O) pad of the IC.
4. The DLL of claim 1 , wherein the reference clock input of the selector is coupled to an input/output (I/O) pad of the IC.
5. The DLL of claim 1 , wherein the reference clock input of the selector is coupled to a second delay-locked loop (DLL) on the IC, and wherein the reference clock corresponds to an output DLL clock of the second DLL.
6. The DLL of claim 1 , wherein the reference clock input is coupled to a phase-locked loop (PLL) on the IC, and wherein the reference clock corresponds to an output dock of the PLL.
7. The DLL of claim 1 , wherein the test clock corresponds to a reference clock of a second DLL.
8. The DLL of claim 1 , further comprising:
a second selector having first and second inputs and an output, the first and second inputs of the second selector receiving the feedback clock, the output of the second selector being coupled to the second input of the phase comparator, wherein the feedback clock is provided by the second selector to the phase comparator when the DLL is in a normal operation mode and when the DLL is in a test mode.