Failure analyzing system and method for displaying the failure

1. A failure analyzing system for displaying a position of a failure in a semiconductor device, comprising:

a circuit position memory operable to store physical positions of respective circuits included in the semiconductor device;

a defective information acquisition unit operable to acquire information on a defective circuit included in the semiconductor device; and

a display operable to display the defective circuit on a layout of the semiconductor device with a color that is different between the physical positions.

2. A failure analyzing system as claimed in claim 1 , wherein said defective circuit information acquisition unit acquires a failure classification of the defective circuit included in the semiconductor device, and

said display displays the defective circuit on a layout of wafer including layouts of a plurality of semiconductor devices with a color that is different between the physical positions and failure classifications.

3. A failure analyzing system as claimed in claim 1 , wherein said circuit position memory further stores, for respective semiconductor devices on wafer, physical positions on the wafer of the semiconductor devices, and

said display displays the defective circuit on a layout of the wafer including layouts of a plurality of semiconductor devices with a color that is different between the physical positions.

4. A failure analyzing system as claimed in claim 3 , wherein said circuit position memory stores for each of circuits included in a multilayer semiconductor device a layer in which the circuit is formed, and

said display displays the defective circuit with a color depending on a layer in which the defective circuit is formed.

5. A failure analyzing system as claimed in claim 4 , wherein said circuit position memory stores for each of wirings included in the semiconductor device a layer in which the wiring is formed,

said defective circuit information acquisition unit acquires information on a defective wiring included in the semiconductor device, and

said display displays the defective wiring with a color that is different depending on a layer in which the defective wiring is formed.

6. A failure analyzing system as claimed in claim 3 , wherein said display displays layouts of a plurality of plates of wafer managed in the same lot while arranging the layouts on one display screen, and displays defective circuits of the plurality of semiconductor devices included in each of the plurality of plates of wafer on a layout of the wafer with colors that depend on physical positions of the defective circuits.

7. A failure analyzing system as claimed in claim 3 , wherein said display displays layouts of a plurality of plates of wafer managed by the same slot in different lots while arranging them on one display screen, and displays defective circuits of a plurality of semiconductor devices included in each of the plurality of plates of wafer on a layout of that wafer with colors depending on physical positions of the defective circuits.

8. A failure analyzing system as claimed in claim 1 , further comprising:

a user interface operable to allow a user to select the defective circuit displayed by the display on the layout of the semiconductor device; and

a test-execution instruction unit operable to instruct a semiconductor test device to execute a more detailed test for the defective circuit selected by the user, wherein

said defective circuit information acquisition unit acquires information on the defective circuit, that was obtained by the more detailed test by said semiconductor test device, and

said display displays the defective circuit on the layout of the semiconductor device with a color that is different between the physical positions.

9. A failure analyzing system for displaying a position of a failure in a multilayer semiconductor device, comprising:

a circuit position memory operable to store, for each of circuits included in the semiconductor device, a layer in which the circuit is formed;

a defective circuit information acquisition unit operable to acquire information on a defective circuit included in the semiconductor device; and

a display operable to display the defective circuit on a layout of the semiconductor device in a display format that is different between the layers.

10. A failure analyzing system as claimed in claim 9 , wherein said defective circuit information acquisition unit acquires a failure classification of the defective circuit included in the semiconductor device, and

said display displays the defective circuit on the layout of the semiconductor device in the display format that is different depending on a layer in which the defective circuit is formed and the failure classification of the defective circuit.

11. A failure analyzing system as claimed in claim 9 , wherein said circuit position memory further stores, for respective semiconductor devices, physical positions in wafer of the semiconductor devices and

said display displays the defective circuit on a layout of the wafer including layouts of the semiconductor devices in the display format that is different between physical positions.

12. A failure position displaying method for displaying a position of a failure in a semiconductor device, comprising:

acquiring information on a defective circuit included in the semiconductor device;

referring to a circuit position memory operable to store physical positions in the semiconductor device of respective circuits included in the semiconductor device and searching a physical position of the defective circuit; and

displaying the defective circuit on a layout of the semiconductor device with a color that is different between the physical positions.

13. A failure position displaying method for displaying a position of a failure in a multilayer semiconductor device, comprising:

acquiring information on a defective circuit included in the semiconductor device;

referring to a circuit position memory operable to store for respective circuits included in the semiconductor device layers in which the respective circuits are formed and searching a layer in which the defective circuit is formed; and

displaying the defective circuit on a layout of the semiconductor device in a display format that is different between the layers.