Compressed memory architecture for embedded systems
An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.
1. A system comprising:
a processor;
a random access memory adapted to store a plurality of frames, wherein each frame is subdivided into a fixed number of subframes, and wherein a mapping table is used to associate each frame with locations in the memory of the fixed number of subframes; and
a buffer and compression engine interposed between the memory and any caches in the processor, the buffer storing one or more uncompressed frames, said uncompressed frames having a size sufficiently large to be efficiently compressed by the compression engine and at least a portion of which is stored in compressed format in the memory, wherein the compression engine is adapted to compress a fixed size frame into a variable length compressed frame, and wherein each variable length compressed frame is stored in a number of subframes that is equal to or less than the fixed number of subframes and indexed using the mapping table.
2. The system of claim 1 wherein, if there is a buffer miss, a compressed frame stored in the memory can be decompressed by a decompression engine and placed in the buffer.
3. The system of claim 1 wherein the buffer is a unified buffer that stores both uncompressed code and uncompressed data.
4. The system of claim 1 wherein the buffer further comprises multiple buffer lines having a first separate buffer for uncompressed code and a second separate buffer for uncompressed data.
5. The system of claim 4 wherein the compression engine uses a different compression algorithm for compressing code and for compressing data.
6. The system of claim 1 wherein the compression engine subdivides each compressed frame into a plurality of fixed size subframes stored in the memory.
7. The system of claim 1 wherein the compression engine uses a dictionary-based algorithm and incorporates run-length encoding.
8. The system of claim 1 wherein the system is an embedded system.
9. An embedded system architecture comprising:
random-access memory which is adapted to store a plurality of frames, wherein each frame is subdivided into a fixed number of subframes and wherein a mapping table is used to associate each frame with locations in memory of the fixed number of subframes; and,
a compressor coupled to the memory which is adapted to compress a fixed size frame into a variable length compressed frame wherein each variable length compressed frame is stored in a number of subframes that is equal to or less than the fixed number of subframes and indexed using the mapping table.
10. The embedded system architecture of claim 9 wherein a frame can contain instruction code or data.
11. The embedded system architecture of claim 9 wherein each subframe is aligned on a fixed size boundary in the memory.