Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses
View Patent ↗A memory interface system and method are provided for transferring data between a memory controller and an array of storage elements. The storage elements are preferably SRAM elements, and the memory interface is preferably one having separate address bus paths and separate data bus paths. One address bus path is reserved for receiving read addresses and the other address bus path is reserved for receiving write addresses. One of the data bus paths is reserved for receiving read data from the array, and the other data bus path is reserved for receiving data written to the array. While bifurcating the address and data bus paths within the interface is transparent to the memory controller, the separate paths afford addressing phases of a read and write address operation to be partially overlapped, as well as the data transfer phases. This will essentially reduce the cycle time between a read and write memory access, and proves useful when maximizing the data throughput across the data bus when implementing double data rate (QDR) mechanisms.
1. A memory interface system for addressing an array of storage elements, comprising:
a first latch coupled to receive a read address and a write address;
a first path and a second path coupled to an output of the latch for receiving respective said read address and said write address;
a storage device coupled to the second path; and
a multiplexer having a first input coupled to the first path and a second input coupled to the second path for sending the read address into the array before sending the write address stored by the storage device into the array.
2. The system as recited in claim 1 , wherein the first and second paths receive respective said read address and said write address during successive portions of a clock cycle.
3. The system as recited in claim 1 , wherein the array of storage elements are coupled to a plurality of word line driver inputs.
4. The system as recited in claim 3 , wherein the multiplexer comprises a plurality of output conductors directly coupled to the plurality of word line driver inputs for receiving the read address before receiving the write address.
5. The system as recited in claim 1 , wherein the first and second paths each comprises a pre-decoder and a buffer, and wherein the write address is sent through the pre-decoder and the buffer upon the second path from the storage device and held within a second latch whose output is directly coupled to the second input upon the first input receiving the read address.
6. The system as recited in claim 1 , wherein the first input and the second input are coupled to receive the write address before a read enable signal is received upon a select pin of the multiplexer.
7. The system as recited in claim 1 , wherein the storage device comprises a set of registers.
8. A method for accessing an array of storage elements, comprising:
storing upon an input to a multiplexer a write address sent over a write address path;
sending upon another input to the multiplexer a read address sent over a read address path in parallel with the write address path;
sensing read data from the array of storage elements sent across a read data path read data accessed by the read address; and
while sensing read data, sending write data across a write data path to be written to the array at the write address.
9. The method as recited in claim 8 , wherein said storing comprises holding the write address held within a set of registers.
10. The method as recited in claim 8 , further comprising forwarding the read address from the multiplexer before forwarding the write address.
11. The method as recited in claim 8 , further comprising forwarding the read address from the multiplexer while storing upon an input to the multiplexer the write address.
12. The method as recited in claim 8 , wherein said sensing comprises storing the sensed read data in an output buffer while sending the write data across the write data path.
13. The method as recited in claim 8 , further comprising storing the write data into a set of registers coupled to the write data path while storing the sensed read data in an output buffer coupled to the read data path.
14. The method as recited in claim 8 , further comprising selecting complementary bit lines for sending the write data from the write data path while outputting the read data from the read data path.
15. The method as recited in claim 8 , wherein said sensing read data comprises sensing a voltage difference between complementary pairs of bit line values stored in the array, and wherein said sending write data comprises driving complementary pairs of bit line values onto the array.