IP Library Granted Patent US 7,606,983
Granted Patent B2
US 7,606,983 · App. 10/873,894 · Granted Oct 20, 2009

Sequential ordering of transactions in digital systems with multiple requestors

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,606,983
App. No.
10/873,894
Granted
Oct 20, 2009
Kind
B2
Abstract

A digital system with an improved transaction ordering policy is disclosed. Individual occurrences of requests for access to common system resources specify whether or not the request is ordered. In some embodiments, the invention includes a memory that holds data, a controller, and at least two processors that generate requests to access the memory data. Each access request includes an indication of whether or not this request is to be performed in a sequential order among other access requests and, if so, an indication of the order. The controller receives the access requests from each processor, determines a performance order for the requests, and provides the access requests to the memory in the performance order. The performance order conforms to the specified order when the access requests so indicate.

Claims (17)

1. A system for processing information, the system comprising: a memory configured to hold data; at least two processors, each configured to perform operations, and to generate an access request when one of the operations involves access to the data, wherein each access request includes an indication of whether or not this occurrence of the access request is to be performed in a sequential order among other occurrences of the access request and, if so, an indication of a specified order; and a controller configured to receive the access requests from each of the processors, to determine a performance order for the access requests, and to provide the access requests to the memory in the performance order, wherein the performance order conforms to the specified order when the access requests indicate the specified order.

2. The system of claim 1 , wherein the memory is selected from a local memory, an embedded memory, an interface to a remote memory, a mum memory, a video memory, a frame buffer memory, a communication buffer, a double data rate (DDR) memory, a random access memory (RAM), a static random access memory (SRAM), or a content addressable memory (CAM).

3. The system of claim 1 , wherein each access request further includes an indication of the type of access to the data, the access type being selected from a read access, a write access, a lookup access, or a move access.

4. The system of claim 1 , wherein each access request further includes an indication of whether or not the access request is the last access request to which the specified order applies.

5. The system of claim 1 , wherein the specified order of a set of access requests corresponds to the order in which the set of access requests is generated.

6. The system of claim 1 , wherein each access request further includes a numerical indication of the position of that access request within the specified order.

7. The system of claim 1 , wherein each access request further includes an indication of a thread identifier (ID), and the specified order applies only to access requests having corresponding thread IDs.

8. The system of claim 1 , wherein: each access request further includes an indication of a thread identifier (ID); a first one of the processors is configured to generate an occurrence of the access request with a specified value for the thread ID; the first processor is further configured to generate an interrupt for a second one of the processors, wherein the interrupt transfers the specified thread ID value to the second processor; the second processor is further configured to generate an occurrence of the access request with the specified thread ID value; and the controller is further configured to compare the thread IDs of each access request, and for a set of access requests having corresponding thread IDs to determine a performance order that conforms to the specified order.

9. A system for processing information, the system comprising: means for accessing data; at least two means for processing series of operations and for generating based thereon access requests for the data, wherein each access request includes an indication of whether or not this occurrence of the access request is to be performed in a sequential order among other occurrences of the access request and, if so, an indication of a specified order; and means for controlling access to the data, for receiving the access requests from each of the processing means, for determining a performance order, and for providing the access requests to the accessing means in the performance order, wherein the performance order conforms to the specified order when the access requests indicate the specified order.

10. The system of claim 9 , wherein: each access request further includes an indication of a thread identifier (ID); a first one of the processing means is a means for generating an occurrence of the access request with a specified value for the thread ID, and is further a means for generating an interrupt of a second one of the processing means, wherein the interrupt transfers to the second processing means the specified thread ID value; the second processing means is a means for generating an occurrence of the access request with the specified thread ID value; and the control means is further means for comparing the thread ID values within each of the access requests and, when the thread ID values of a set of access requests correspond, for generating the performance order such that it conforms with the specified order indicated in the access requests.

11. A method of processing information, the method comprising: holding data; performing in parallel at least two series of operations; generating an access request when performing one of the operations when the operation involves accessing the data; including in each access request an indication of whether or not this occurrence of the access request has a specified order among other occurrences of the access request; including an indication of the specified order in those occurrence of the access request that arc ordered; receiving the access requests from each of the series of operations; determining a performance order for the access requests, wherein if the access requests are ordered then the performance order conforms to the specified order; and performing the access requests in the performance order.

12. The method of claim 11 , further comprising: including in each occurrence of the access request an indication of the type of access to the data, the access type being selected from reading, writing, looking up, and moving.

13. The method of claim 11 , further comprising: including in each access request an indication of whether or not the access request is the last access request to which the specified order applies.

14. The method of claim 11 further comprising: generating a set of access requests is an order that corresponds to the specified order.

15. The method of claim 11 , further comprising: including in each access request a numerical indication of the position of that access request within the specified order.

16. The method of claim 11 , further comprising: including in each access request an indication of a thread identifier (ID), and the specified order applies only to access requests having corresponding thread IDs.

17. The method of claim 11 , further comprising: including in each access request an indication of a thread identifier (ID); generating, based on a first one of the series of operations, a first access request with a specified value for the thread ID; generating, based on the first series of operations, an interrupt for a second one of the series of operations, wherein the interrupt transfers the specified thread ID value to the second series of operations; generating, based on the second series of operations, a second access request with the specified thread ID value; comparing the thread ID values within each of the access requests; and performing a set of access requests in the specified order when the thread ID values of the set of access requests match.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 048387/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2019
From: NXP B.V.
To: VLSI TECHNOLOGY LLC
Reel/Frame 048349/0250 →
CHANGE OF NAME Recorded Sep 22, 2017
From: PHILIPS SEMICONDUCTORS INTERNATIONAL B.V.
To: NXP B.V.
Reel/Frame 043951/0436 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2017
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: PHILIPS SEMICONDUCTORS INTERNATIONAL B.V.
Reel/Frame 043955/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2004
From: LOCKER, KEVIN
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 015512/0595 →