Delay locked loop circuit capable of operating in a low frequency
A delay-locked loop circuit may include a frequency doubler for increasing a frequency of a clock signal and a frequency divider for decreasing the frequency of the clock signal. The delay-locked loop circuit can be selectively operated in a low frequency and a high frequency by the frequency doubler and the frequency divider.
1. A delay locked loop, comprising:
an input buffer for buffering a clock signal;
a first switching circuit for transferring a clock signal outputted from the input buffer in response to a control signal;
a frequency doubler for increasing a frequency of the clock signal transferred from the first switching circuit;
a variable delay line for delaying the clock signal outputted from the frequency doubler or from the first switching circuit;
a second switching circuit for transferring the clock signal from the variable delay line in response to the control signal;
a frequency divider for decreasing the frequency of the clock signal outputted from the second switching circuit;
an output buffer for buffering the clock signal outputted from the second switching circuit or from the frequency divider;
a replica for delaying the clock signal outputted from the variable delay line;
a phase detector for detecting a phase difference between the clock signal outputted from the replica and the clock signal outputted from the frequency doubler or from the first switching circuit; and
a control circuit for determining a delay amount of the variable delay line according to an output signal of the phase detector.
2. The delay locked loop of claim 1 , wherein the replica has a modeling structure of a tAC path.
3. The delay locked loop of claim 1 , comprising a trimming logic unit coupled between the variable delay line and the replica, for adjusting a tAC in a wafer level.
4. The delay locked loop of claim 3 , wherein the trimming logic unit comprises:
a logic circuit for generating a plurality of logic signals;
a decoder for decoding the outputs from the logic circuit; and
a unit delay cell array for delaying the output from the variable delay line according to the outputs from the decoder.
5. The delay locked loop of claim 4 , wherein the logic circuit comprises a plurality of unit logic circuits,
wherein each of the plurality of unit logic circuits comprises:
a fuse coupled between a power terminal and a node;
a capacitor coupled between the node and a ground terminal;
an inverter coupled between the node and an output terminal; and
a transistor coupled between the node and the ground terminal and operated according to a potential of the output terminal.
6. The delay locked loop of claim 4 , wherein the unit delay cell array is dependently coupled between the variable delay line and the replica, and comprised of a plurality of unit delay cells.
7. The delay locked loop of claim 6 , wherein each of the unit delay cells comprises:
a first NAND gate for receiving the output from the variable delay line and the output from the decoder;
a second NAND gate for receiving the output from the preceding unit delay cell and the output from the first NAND gate; and
a third NAND gate for receiving the output from the second NAND gate and power, and outputting the output to the succeeding unit delay cell.
8. The delay locked loop of claim 1 ,
wherein the first switching circuit includes:
a first transfer gate for transferring the clock signal outputted from the buffer to the frequency doubler; and
a second transfer gate for transferring the clock signal outputted from the buffer to the variable delay line,
wherein, the first transfer gate is operated during a test operation and the second transfer gate is operated during a normal operation, in response to the control signal.
9. The delay locked loop of claim 8 , wherein each of the first and second switching circuits comprises transmissions gates.
10. The delay locked loop of claim 1 , wherein the second switching circuit includes:
a first transfer gate for transferring the clock signal outputted from the variable delay line to the frequency divider; and
a second transfer gate for transferring the clock signal outputted from the variable delay line to the output buffer,
wherein, the first transfer gate is operated during a test operation and the second transfer gate is operated during a normal operation, in response to the control signal.
11. A delay locked loop, comprising:
an input buffer for buffering a clock;
a first switch device for switching the output from the input buffer according to a control signal;
a frequency doubler for increasing a frequency of the output from the input buffer passing through the first switch device;
a second switch device for switching the output from the input buffer according to the control signal, the second switch device being operated oppositely to the first switch device;
a variable delay line for delaying the output from the frequency doubler or the output from the input buffer;
a third switch device for switching the output from the variable delay line according to the control signal;
a fourth switch device for switching the output from the variable delay line according to the control signal, the fourth switch device being operated oppositely to the third switch device;
a divider for restoring the output frequency from the variable delay line passing through the third switch device to the frequency of the clock, by dividing the output frequency of the signal from the variable delay line;
an output buffer for buffering the output from the divider or the output from the variable delay line passing through the fourth switch device;
a replica for delaying the output from the variable delay line;
a phase detector for detecting a phase difference between the output from the replica and the output from the frequency doubler; and
a control circuit for determining a delay amount of the variable delay line according to the output from the phase detector.
12. The delay locked loop of claim 11 , wherein the replica has a modeling structure of a tAC path.
13. The delay locked loop of claim 11 , comprising a trimming logic unit coupled between the variable delay line and the replica, for adjusting a tAC in a wafer level.
14. The delay locked loop of claim 13 , wherein the trimming logic unit comprises:
a logic circuit for generating a plurality of logic signals;
a decoder for decoding the outputs from the logic circuit; and
a unit delay cell array for delaying the output from the variable delay line according to the outputs from the decoder.
15. The delay locked loop of claim 14 , wherein the logic circuit comprises a plurality of unit logic circuits,
wherein each of the plurality of unit logic circuits comprises:
a fuse coupled between a power terminal and a node;
a capacitor coupled between the node and a ground terminal;
an inverter coupled between the node and an output terminal; and
a transistor coupled between the node and the ground terminal and operated according to a potential of the output terminal.
16. The delay locked loop of claim 14 , wherein the unit delay cell array is dependently coupled between the variable delay line and the replica, and comprised of a plurality of unit delay cells.
17. The delay locked loop of either claim 16 , wherein each of the unit delay cells comprises:
a first NAND gate for receiving the output from the variable delay line and the output from the decoder;
a second NAND gate for receiving the output from the preceding unit delay cell and the output from the first NAND gate; and
a third NAND gate for receiving the output from the second NAND gate and power, and outputting the output to the succeeding unit delay cell.
18. The delay locked loop of claim 11 , wherein each of the first to fourth switch devices is a transmission gate.