Semiconductor device memory cell
View Patent ↗The present invention provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process, in which a hard mask is formed on the upper surface of the bit line and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film of the conventional semiconductor device which does not have the SAC structure is etched off except the portion where bit line is formed, and then direct nitride film is formed on the entire surface of the top surface and the side surface of the bit line so as to cover the bit line in a same processing step. Since the film thickness of the nitride film disposed on the upper surface of the bit line is designed to be substantially the same as that disposed on the side surface of the nitride film, the height of the bit line itself can be reduced, and thus a further miniaturization becomes possible. In addition, since the nitride film is formed on the side wall of the bit line without requiring an etch back process according to the process of the present invention, the nitride film having a constant film thickness can be easily formed on the side wall of the bit line, as compared with the conventional SAC structure.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first interlayer insulating film on said semiconductor substrate;
a first cell contact plug in said first insulating film;
a first bit line electrically connected to said first cell contact plug;
a barrier film intervening between said first cell contact plug and said first bit line, wherein said barrier film has an inversely-tapered shape; and
a nitride film covering a side surface and an upper surface of said first bit line.
2. The semiconductor device according to claim 1 , further comprising a bit contact plug between said first cell contact plug and said barrier film.
3. The semiconductor device according to claim 1 , further comprising:
a second cell contact plug in said first interlayer insulating film;
a second bit line on said first interlayer insulating film;
a second interlayer insulating film on said nitride film; and
a capacitor contact plug in said second interlayer insulating film and connected to said second cell contact plug between said first bit line and said second bit line.
4. The semiconductor device according to claim 3 , further comprising:
a capacitor element on said second interlayer insulating film, a lower electrode of which being connected to said capacitor contact plug.
5. A semiconductor device comprising:
a semiconductor substrate;
a first interlayer insulating film on said semiconductor substrate;
a first and a second cell contact plug in said first interlayer insulating film;
a first and a second bit line, said first bit line being electrically connected to said first cell contact plug, said second cell contact plug being arranged between said first and second bit lines;
a nitride film covering side surfaces and upper surfaces of said first and second bit lines;
a second interlayer insulating film on said nitride film;
a capacitor contact plug in said second interlayer insulating film and connected to said second cell contact plug between said first bit line and said second bit line;
a capacitor element on said second interlayer insulating film, a lower electrode of which is connected to said capacitor contact plug; and
a barrier film between said first cell contact plug and said first bit line, said barrier film having an inversely-tapered shape.
6. A semiconductor device comprising:
a contact plug;
a bit line electrically connected to said contact plug; and
a barrier film between said contact plug and said bit line, wherein said barner film having an inversely-tapered shape.
7. The semiconductor device according to claim 6 , wherein said bit line has a tapered-shape.
8. The semiconductor device according to claim 7 , further comprising a bit contact plug between said contact plug and said barrier film.