Method, apparatus, and system to enhance negative voltage switching
View Patent ↗The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.
1. A method, comprising:
receiving a signal to erase a first block within a memory array;
lowering an output of a negative charge pump to a negative voltage;
applying the output of the negative charge pump to a word line of the first block; and
pulling up the output of the negative charge pump to apply a read-mode voltage to a memory cell of a second block within the memory array substantially simultaneously with said applying the output.
2. The method of claim 1 , further comprising applying a signal to a word line and a bit line to erase the first block.
3. The method of claim 1 , further comprising applying a signal to a word line and a bit line of the second block to read the memory cell substantially simultaneously with erasing the first block.
4. The method of claim 1 , wherein said receiving a signal to erase a first block within a memory array comprises:
receiving an instruction to erase the first block; and
receiving an instruction to read the memory cell prior to erasure of the first block.
5. The method of claim 1 , wherein said lowering an output of a negative charge pump to a negative voltage comprises lowering the output of the negative charge pump to a high magnitude, negative voltage.
6. The method of claim 1 , wherein said applying the output of the negative charge pump to a source line of the first block comprises coupling the output of the negative charge pump to the source line.
7. The method of claim 1 , wherein said pulling up the output comprises turning off transistors to substantially prevent current burn within a negative level shifter coupled to the second block of memory.
8. The method of claim 1 , wherein said pulling up the output comprises applying a low resistance current to the memory cell.