Memory device having a P+ gate and thin bottom oxide and method of erasing same
View Patent ↗A non-volatile memory device includes a semiconductor substrate and an N-type source and drain within the substrate. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a thin bottom oxide layer. A P + polysilicon gate electrode is formed over the ONO stack. The memory device is operative to perform a channel erase operation in which a pair of charge storing cells within the nitride layer are erased simultaneously.
1. A memory device comprising:
a semiconductor substrate:
an N-type conductivity source and an N-type conductivity drain formed on opposite sides within the semiconductor substrate, said source and drain defining a body region therebetween;
a bottom dielectric layer formed over the semiconductor substrate, said bottom dielectric layer having a thickness;
a charge storing layer formed over the bottom dielectric layer, said charge storing layer having a conductivity such that a first charge can be stored in a first charge storing cell adjacent the source and a second charge can be stored in a second charge storing cell adjacent the drain;
a top dielectric layer formed over the charge storing layer, said top dielectric having a thickness, wherein the thickness of the bottom dielectric layer is less than the thickness of the top dielectric layer; and
a P + polysilicon gate electrode formed over the top dielectric layer.
2. The memory device according to claim 1 , wherein the bottom dielectric layer has a thickness of about 40 Å to about 60Å.
3. The memory device according to claim 2 , wherein the top dielectric layer has a thickness of about 100 Å to about 120 Å.
4. The memory device according to claim 2 , wherein the charge storing layer has a thickness of about 40 Å to about 70 Å.
5. The memory device according to claim 1 , wherein the P − polysilicon gate electrode is effective to decrease the probability that, during an erase operation, electrons within the gate layer will overcome a potential barrier of the top dielectric layer and enter the charge storing layer.
6. The memory device according to claim 5 , wherein the bottom dielectric layer is effective to (i) increase the probability that, during an erase operation, electrons within the charge storing layer will overcome a potential barrier of the bottom dielectric layer to exit the charge storing layer into the substrate, and (ii) decrease the probability that, during operations other than an erase operation, electrons will overcome a potential barrier of the bottom dielectric layer and escape from the charge storing layer.
7. The memory device according to claim 2 , wherein the P − polysilicon gate layer and the bottom dielectric layer are effective to increase the probability that electrons will be removed from the charge storing layer via a channel erase operation.
8. The memory device according to claim 1 , wherein the gate electrode has a P + dopant concentration of about 1×e 19 atoms/cm 3 to about 1×e 21 atoms/cm 3.
9. A method of performing an erase operation on the memory device according to claim 1 , the method comprising:
applying a negative erase voltage to the gate electrode;
one of (i) connecting the drain to a zero potential, and (ii) floating the drain; and
one of (i) connecting the source to a zero potential and (ii) floating the source.
10. The method according to claim 9 , wherein the simultaneous steps occur for a duration of at least about 100 ms.
11. The method according to claim 10 , wherein the erase voltage applied to the gate electrode is in a range of about −10 volts to about −20 volts.
12. The method according to claim 10 , wherein the erase voltage applied to the gate electrode is less than about −20 volts.
13. The method according to claim 10 , wherein the duration is less than about 1 sec.
14. The method according to claim 10 , wherein the charge storing layer includes two bits, both bits being erased simultaneously.
15. A memory device comprising:
a semiconductor substrate having a first conductive region and a second conductive region formed therein and a channel region interposed between the first and second conductive regions;
a first dielectric layer disposed over the semiconductor substrate;
a dielectric charge trapping layer disposed over the first dielectric layer;
a second dielectric layer disposed over the dielectric charge trapping layer; and
a gate electrode disposed over the second dielectric layer, wherein the gate electrode has a barrier height of about 4.1 eV to about 4.2 eV relative to the second dielectric layer.
16. The memory device according to claim 15 , wherein the gate electrode is comprised of P + polysilicon.
17. The memory device according to claim 15 , wherein the second dielectric layer has a thickness that is less than a thickness of the first dielectric layer.
18. The memory device according to claim 17 , wherein the second dielectric layer has a thickness of about 40 Å to about 60 Å.
19. The memory device according to claim 18 , wherein the first dielectric layer has a thickness of about 100 Å to about 120 Å.