Transistor of semiconductor device and method for manufacturing the same
Transistor of semiconductor device and method for manufacturing the same are disclosed. The transistor comprises a channel region formed on a sidewall of a silicon fin extruding above a device isolation region. The silicon fin serves as an active region and is shorter in length so as to be spaced apart from an adjacent gate electrode. The width of the channel region is determined by the height of the silicon fin. The source/drain region of the transistor is disposed at an upper surface and the sidewall of the silicon fin to increase the contact region.
1. A method for manufacturing transistor of semiconductor device, the method comprising the steps of:
(a) forming a trench type device isolation film defining a I-type active region on a semiconductor substrate having a stacked structure of a pad oxide film, a pad nitride film thereon;
(b) etching a predetermined thickness of the device isolation film to form a silicon fin extruding above the device isolation film;
(c) tilt implanting an impurity on a sidewall of the silicon fin to form a channel region;
(d) forming a gate oxide film on the sidewall of the silicon fin;
(e) forming a planarized polysilicon layer for gate electrode on the semiconductor substrate;
(f) patterning the polysilicon layer and the pad nitride film to form a gate electrode;
(g) forming a lower insulating film including a landing plug contact hole exposing a portion of the pad oxide film and a portion of the gate oxide film;
(h) performing an ion implant process to form an impurity implanted region at a bottom of the landing plug contact hole;
(i) etching the exposed portion of the pad oxide film to expose the silicon fin; and
(j) forming a landing plug filling the landing plug contact hole.
2. The method according to claim 1 , wherein the step (a) comprises:
forming the stacked structure of the pad oxide film and the pad nitride film on the semiconductor substrate;
performing an exposure and development process using an exposure mask having a mask film pattern defining the I-type active region spaced apart from a region where the gate electrode is to be formed to form a photoresist film pattern on the semiconductor substrate;
forming a trench by etching the stacked structure and the semiconductor substrate using the photoresist film pattern as an etching mask; and
forming the trench type device isolation film by filling the trench.
3. The method according to claim 1 , wherein the step (a) comprises:
forming the stacked structure of the pad oxide film and the pad nitride film on the semiconductor substrate;
forming a CVD oxide film on the pad nitride film;
etching the CVD oxide film via a photolithography process using a device isolation film mask to form a CVD oxide film pattern;
wet etching the surface of the CVD oxide film pattern;
forming a trench by etching the pad nitride film, the pad oxide film and the semiconductor substrate using the wet-etched CVD oxide film pattern as an etching mask; and
forming the trench type device isolation film by filling the trench.
4. The method according to claim 1 , wherein the step (a) comprises:
forming the stacked structure of the pad oxide film and the pad nitride film on the semiconductor substrate;
etching the pad nitride film via a photolithography process using a device isolation film mask to form a pad nitride film pattern;
wet etching the surface of the pad nitride film pattern;
forming a trench by etching the pad oxide film and the semiconductor substrate using pad nitride film pattern as an etching mask; and
forming the trench type device isolation film by filling the trench.
5. The method according to claim 2 , wherein the trench formation process further comprises forming a thermal oxide film and a liner nitride film on the surface of the trench.
6. The method according to claim 1 , wherein the tilt implanting process of the step (c) is performed at an impurity concentration ranging from 10E10 to 10E19/cm 3 .
7. The method according to claim 1 , wherein the gate oxide film has a thickness ranging from 50 to 100 Å.
8. The method according to claim 1 , wherein the step (h) comprises:
forming a LDD region by ion-implanting an impurity for LDD at the bottom of the landing plug contact hole; and
forming a halo impurity region by ion-implanting a halo impurity.
9. The method according to claim 1 , wherein the method comprises diffusing an impurity included the landing plug into the silicon fin to form a source/drain region.
10. The method according to claim 1 , wherein the gate electrode further comprises a stacked structure of a barrier metal layer, a metal layer, a hard mask nitride film and a hard mask oxide film.
11. The method according to claim 1 , wherein the step (g) comprises:
forming a nitride film for spacer on the semiconductor substrate;
forming a planarized insulating film on the nitride film for spacer; and
performing a SAC process to form a nitride spacer and the landing plug contact hole.
12. The method according to claim 11 , wherein the SAC process comprises an over-etch process for removing the pad nitride film and the nitride film for spacer on the gate oxide film.
13. The method according to claim 1 , wherein the pad oxide film has a thickness ranging from 50 to 200 Å.
14. The method according to claim 1 , wherein the pad nitride film has a thickness ranging from 100 to 400 Å.
15. The method according to claim 3 , wherein the trench formation process further comprises forming a thermal oxide film and a liner nitride film on the surface of the trench.
16. The method according to claim 4 , wherein the trench formation process further comprises forming a thermal oxide film and a liner nitride film on the surface of the trench.