Data output apparatus for memory device
A data output circuit for a memory device improves data transfer speed from the memory device by re-amplifying stored data using by a bitline sense amplifier and transferring it to global input/output lines. Data read from the memory device is coupled to an amplifier interposed between the first and second “local” data lines. CMOS buffers receive data on first and second local data lines and outputs the data to first and second latches, the outputs of which are coupled to the inputs of a series connected pull-up transistor and a pull-down transistor coupled between a driving voltage and a ground terminal in series.
1. A data output apparatus for a memory device, comprising:
first and second local data lines for receiving data transferred from a pair of bitlines of;
an amplifier interposed between the first and second local data lines;
a first CMOS buffer means for receiving data on the first local data line;
a second CMOS buffer means for receiving data on the second local data line;
a first latch means for holding an output signal of the first CMOS buffer means;
a second latch means for holding an output signal of the second CMOS buffer means; and
a pull-up transistor and a pull-down transistor coupled in series between a driving voltage and a ground terminal;
a first switch coupled between an input unit of the first latch means and a ground terminal;
a second switch coupled between an input unit of the second latch means and the ground terminal;
wherein, during a standby mode, the first and second switches are turned on thereby coupling the input units of the first and second latch means to the ground terminal and during an operating mode, the first and second switches are continually turned off;
and wherein an output signal of the first latch means is applied to a gate of the pull-up transistor, while an output signal of the second latch means is applied to a gate of the pull-down transistor.
2. The data output apparatus of claim 1 , wherein the amplifier and the first and second CMOS buffer means are enabled by a first control signal, and
the enabled amplifier amplifies the data on the first and second local data lines, transferring them to the first and second CMOS buffer means.
3. The data output apparatus of claim 1 , wherein during an operating mode, the first control signal is enabled after the first and second switches are turned off.
4. The data output apparatus of claim 1 , wherein the first and second switches comprise MOS transistors and are turned on/off according to a second control signal applied to a gate of each MOS transistor.
5. The data output apparatus of claim 4 , wherein the amplifier and the first and second CMOS buffer means are enabled by the first control signal, after the first and second switches are turned off by the second control signal.
6. The data output apparatus of claim 1 , wherein the first CMOS buffer means receive the data on the first local data line, thereto inverting it; and
the second CMOS buffer means receives the data on the second local data line, thereto inverting it.
7. The data output apparatus of claim 1 , wherein during an operating mode, the data on the first local data line has an opposite logical level to the data on the second data line.