Method for manufacturing flash memory device
The present invention discloses a method for manufacturing a flash memory device, including the steps of: forming gate electrode patterns on a semiconductor substrate on which a high voltage region and a low voltage region are defined; forming a first mask pattern for simultaneously exposing the high voltage region and the low voltage region, and forming junction regions in the high voltage region and the low voltage region at the same time by performing a first ion implant process; removing the first mask pattern for simultaneously exposing the high voltage region and the low voltage region, and forming spacers on each gate electrode pattern; forming a second mask pattern for simultaneously exposing the high voltage region and the low voltage region; and forming LDD regions in the junction region of the high voltage region and the junction region of the low voltage region at the same time by performing a second ion implant process.
1 . A method for manufacturing a flash memory device, comprising the steps of:
forming gate electrode patterns on a semiconductor substrate on which a high voltage region and a low voltage region are defined;
forming a first mask pattern for simultaneously exposing the high voltage region and the low voltage region, and forming junction regions in the high voltage region and the low voltage region at the same time by performing a first ion implant process;
removing the first mask pattern for simultaneously exposing the high voltage region and the low voltage region, and forming spacers on each gate electrode pattern;
forming a second mask pattern for simultaneously exposing the high voltage region and the low voltage region; and
forming LDD regions in the junction region of the high voltage region and the junction region of the low voltage region at the same time by performing a second ion implant process.
2 . The method of claim 1 , after the step of forming the LDD regions, further comprising the steps of:
forming an interlayer insulation film on the whole surface of the resulting structure; and
forming contact plugs contacting the LDD regions of the high voltage region and the low voltage region.
3 . The method of claim 1 , wherein the first ion implant process is performed by implanting P ions and As ions.
4 . The method of claim 1 , wherein the second ion implant process is performed by implanting As ions.
5 . A method for manufacturing a flash memory device, comprising the steps of:
forming gate electrode patterns on a semiconductor substrate on which a high voltage region and a low voltage region are defined;
forming a first mask pattern for simultaneously exposing the high voltage region and the low voltage region, and forming junction regions in the high voltage region and the low voltage region at the same time by performing a first ion implant process;
removing the first mask pattern for simultaneously exposing the high voltage region and the low voltage region, and forming spacers on each gate electrode pattern;
forming a second mask pattern for simultaneously exposing the high voltage region and the low voltage region; and
forming LDD regions in the junction region of the high voltage region and the junction region of the low voltage region at the same time by performing a second ion implant process;
forming an interlayer insulation film on the whole surface of the resulting structure; and
forming contact plugs contacting the LDD regions of the high voltage region and the low voltage region.
6 . The method of claim 5 , wherein the first ion implant process is performed by implanting P ions and As ions.
7 . The method of claim 6 , wherein the second ion implant process is performed by implanting As ions.