Flash memory device and method for fabricating the same, and programming and erasing method thereof
View Patent ↗A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on the ONO layer; second and third control gates on the ONO layer at both sides of the first control gate; and source and drain regions in the surface of the semiconductor substrate at both sides of the second and third control gates.
1. A programming method of a flash memory device of SONOS structure, the flash memory device including second and third control gates at both sides of a first control gate, source and drain regions in a surface of a semiconductor substrate at both sides of the second and third control gates, and ONO layers between the control gates and the semiconductor substrate, comprising:
a first step of applying a high voltage pulse to the first and third control gates, and trapping hot electrons to the ONO layer around the drain region; and
a second step of annealing the trapped electrons by applying a high voltage pulse to the first control gate.
2. The programming method of claim 1 , wherein in the first step, 0V is applied to the source region, a voltage over a threshold voltage is applied to the second control gate, a voltage pulse of 10V or more is applied to the first and third control gates, and a voltage of 4V or more is applied to the drain region.
3. The programming method of claim 1 , wherein, in the second step, 0V is applied to the source and drain region, a voltage of −4V is applied to the second and third control gates, and a voltage pulse of −10V is applied to the first control gate.
4. The programming method of claim 1 , further comprising a third step of trapping hot electrons to the ONO layer around the source region by applying a high voltage pulse to the first and second control gates.
5. An erasing method of flash memory device of SONOS structure, the flash memory device including second and third control gates at both sides of a first control gate, source and drain regions in a surface of a semiconductor substrate at both sides of the second and third control gates, and ONO layers between the control gates and the semiconductor substrate, comprising:
a first step of injecting a hole to the ONO layer around the source or drain region by applying a negative voltage to the second and third control gate; and
a second step of annealing the injected hole by applying a positive high voltage pulse to the first control gate, and applying a negative high voltage pulse to the second and third control gates.
6. The erasing method of claim 5 , wherein, in the first step, a voltage over 0V or 5V is applied to the source or drain region, a voltage over a threshold voltage is applied to the second or third control gate, and a voltage pulse of −3V or more is applied to the first/third or second control gate.
7. The erasing method of claim 5 , wherein, in the second step, 0V is applied to the source and drain regions, a voltage pulse of 10V is applied to the second and third control gates, and a voltage pulse (several tens ms) of −10V is applied to the first control gate, thereby removing electrons moved to a lateral side.