Flash memory cell and method of erasing the same
Provided is related to a flash memory cell and method of erasing the same. A P-type well field-effective flash cell is comprised of a drain formed in a P-type semiconductor substrate, a channel region made of a triple N-well, a source of P-well formed in the triple N-well, a floating gate formed on the channel region, a tunnel oxide film formed under the floating gate, a control gate formed with a predetermined pattern on the overall structure including the floating gate, and a dielectric film formed under the control gate. When the flash cell is turned on at a predetermined threshold voltage to drop a P-well bias, an electric field between the floating gate and the semiconductor substrate weakens to inhibit electron injection that is caused by F-N tunneling effect and thereby an erased threshold voltage goes to a target voltage.
1 . A flash memory cell comprising:
a drain formed in a P-type semiconductor substrate;
a channel region made of a triple N-well;
a source of a P-well formed in the triple N-well;
a floating gate formed on the channel region;
a tunnel oxide film formed under the floating gate;
a control gate formed with a predetermined pattern on the overall structure including the floating gate; and
a dielectric film formed under the control gate.
2 . The flash memory cell as set forth in claim 1 , wherein an edge of the floating gate is overlapped with the source and the drain.
3 . The flash memory cell as set forth in claim 1 , further comprising a poly-silicon layer interposed between the tunnel oxide film and the dielectric film over the P-well.
4 . The flash memory cell as set forth in claim 1 , further comprising a poly-silicon layer interposed between the tunnel oxide film and the dielectric film over the drain.
5 . The flash memory cell as set forth in claim 1 , wherein the tunnel oxide film is a field isolation film formed by a LOCOS process or a field isolation film constructed of a STI structure.
6 . The flash memory cell as set forth in claim 5 , wherein a thickness of the field isolation film is 200 nm through 300 nm.
7 . A method of erasing a flash memory cell, comprising:
applying a negative erasing voltage to a control gate; and
applying a positive erasing voltage to a P-well;
whereby charges accumulated in a floating gate of a flash memory cell described in claim 1 are discharged from the floating gate.
8 . The method as set forth in claim 7 , wherein the negative erasing voltage is −5V through −20V.
9 . The method as set forth in claim 7 , wherein the positive erasing voltage is 5V through 20V.
10 . The method as set forth in claim 7 , wherein a positive voltage is applied to the triple N-well to retain the positive erasing voltage, which is applied to the P-well, in a P-N diode mode, during applying the erasing voltage.
11 . The method as set forth in claim 10 , wherein a voltage higher than a voltage applied to the P-well is applied to the triple N-well.
12 . The method as set forth in claim 11 , wherein a voltage higher than a voltage applied to the P-well, by 0V through 5V, is applied to the triple N-well.