IP Library Granted Patent US 7,166,866
Granted Patent B2
US 7,166,866 · App. 10/882,387 · Granted Jan 23, 2007

Edge termination for silicon power devices

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Quick Facts
Patent No.
US 7,166,866
App. No.
10/882,387
Granted
Jan 23, 2007
Kind
B2
Abstract

A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer. A well region of a second, opposite conduction type is formed at the upper surface of the upper layer adjacent the edge termination zone, and an oxide layer is formed over the upper layer and edge termination zone.

Claims (13)

1. A device in an integrated circuit comprising:

a silicon substrate of a first conductivity type having an upper surface;

at least a first region in the upper surface of the substrate being of a material having a higher critical field than the silicon;

a second region of silicon and of a second conductivity type opposite of the first conductivity type in the upper surface of the substrate: and

wherein the first region is at and forms an edge termination of the junction of the second region and the substrate.

2. The device according to claim 1 , wherein the material of the first region includes carbon.

3. The device according to claim 1 , wherein the material of the first region includes silicon carbide.

4. The device according to claim 1 , wherein the material of the first region is formed by ion implantation into the substrate.

5. The device according to claim 4 , wherein carbon is ion implanted.

6. The device according to claim 1 , wherein the material of the first region is formed by selective deposition.

7. The device according to claim 1 , wherein the material of the first region is formed by selective epitaxial deposition.

8. The device according to claim 1 , wherein the first region overlaps the junction the second region and the substrate.

9. The device according to claim 1 , wherein the first region is in a recess in the top surface of the substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: ZENG, JUN; SHENOY, PRAVEEN MURALEEDHARAN; DOLNY, GARY M
To: INTERSIL CORPORATION
Reel/Frame 036868/0708 →
SECURITY AGREEMENT Recorded May 5, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.; ZILKER LABS, INC.; KENET, INC.; INTERSIL AMERICAS INC.; ELANTEC SEMICONDUCTOR, INC.; D2AUDIO CORPORATION; PLANET ATE, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024329/0831 →