Method for manufacturing flash memory device
View Patent ↗The present invention discloses a method for manufacturing a flash memory device which can minimize a hole current by impurity diffusion of floating gates, obtain a sufficient capacitance for a cell operation by increasing a breakdown voltage, and improve retention properties of a flash memory cell, by filing up an impurity on the interface between an oxide film and a polysilicon film, by forming the oxide film on the polysilicon film used as the floating gates, doping an impurity into the oxide film, and annealing the oxide film.
1. A method for manufacturing a flash memory device, comprising the steps of:
forming a tunnel oxide film and a first polysilicon film on a semiconductor substrate;
forming an oxide film on the first polysilicon film;
distributing an impurity along the interface between the first polysilicon film and the oxide film by doping the impurity into the oxide film and annealing the oxide film;
forming a dielectric film on the oxide film; and
forming a second polysilicon film and a tungsten silicide film over the resulting structure, and performing an etching process thereon.
2. The method of claim 1 , wherein the first polysilicon film comprises 1E20 cm −3 to 5E21 cm −3 of a dopant selected from the group consisting of P and As.
3. The method of claim 1 , wherein the step of forming the first polysilicon film comprises forming a doped polysilicon film or forming an undoped polysilicon film and then doping the undoped polysilicon film with a dopant selected from the group consisting of P and As according to a plasma process or an annealing process.
4. The method of claim 1 , wherein the first polysilicon film comprises a merged PIN/Schottky structure.
5. The method of claim 1 , wherein the step of forming the oxide film comprises cleaning the first polysilicon film with a standard clean #1 solution, a dry oxidation process, or a wet oxidation process.
6. The method of claim 5 , wherein the dry oxidation process is performed for 3 to 120 minutes at a temperature of 500 to 800° C. under a pressure of 0.05 to 760 Torr in a gas atmosphere comprising oxygen-containing molecules.
7. The method of claim 6 , wherein: (a) the oxygen-containing molecules are selected from the group consisting of O 2 , N 2 O, NO, O 3 , H 2 O, and combinations thereof; and, (b) the gas atmosphere optionally comprises Ar.
8. The method of claim 5 , wherein the wet oxidation process is performed for 1 to 30 minutes at a normal temperature or a temperature of 80° C. in an aqueous solution obtained by mixing NH 4 OH and H 2 O 2 at a predetermined ratio.
9. The method of claim 1 , wherein the oxide film has a thickness of 5 to 25Å.
10. The method of claim 1 , wherein the impurity is doped in a gas atmosphere including elements having a higher valence than silicon.
11. The method of claim 10 , wherein: (a) the elements having a higher valence than silicon comprise a member selected from the group consisting of P in the form of PH 3 and As in the form of AsH 3 , and (b) the gas atmosphere optionally comprises Ar.
12. The method of claim 1 , wherein the annealing process is performed as an in-situ process after doping the impurity.
13. The method of claim 1 , wherein the annealing process is performed for 3 to 180 minutes at a temperature of 500 to 800° C. under a pressure of 0.05 to 760 Torr in NH 3 atmosphere.
14. The method of claim 1 , wherein the dielectric film has a stacked structure of a lower oxide film, a nitride film and an upper oxide film.
15. The method of claim 14 , wherein the lower oxide film and the upper oxide film are formed according to a chemical vapor reaction using a mixed gas of SiH 4 and N 2 O or a mixed gas of SiH 2 Cl 2 and N 2 O at a temperature of 700 to 900° C. under a pressure of 0.05 to 3 Torr.
16. The method of claim 14 , wherein the nitride film is formed according to a chemical vapor reaction using a mixed gas of SiH 4 and NH 3 or a mixed gas of SiH 2 Cl 2 and NH 3 at a temperature of 600 to 800° C. under a pressure of 0.05 to 3 Torr.
17. The method of claim 14 , wherein the nitride film is formed by nitrifying the surface of the lower oxide film by using a single gas of NH 3 , a mixed gas of NH 3 and Ar, or a mixed gas of NH 3 and N 2 at a temperature of 600 to 800° C. under a pressure of 20 to 760 Torr.
18. The method of claim 14 , wherein the nitride film comprises a primary nitride film formed by nitrifying the lower oxide film and a secondary nitride film formed by a chemical vapor reaction.
19. The method of claim 1 , further comprising a steam annealing process after forming the dielectric film.
20. The method of claim 19 , wherein the steam annealing process is performed for 3 to 120 minutes at a temperature of 750 to 850° C. under a pressure of 0.05 to 760 Torr by using a gas comprising oxygen-containing molecules.
21. The method of claim 20 , wherein: (a) the oxygen-containing molecules are selected from the group consisting of O 2 , N 2 O, NO, O 3 , H 2 O, and combinations thereof; and, (b) the gas optionally comprises Ar.
22. The method of claim 19 , wherein the steam annealing process is performed on a single crystal wafer cleaned in an aqueous solution containing HF to grow the oxide film at a thickness of 50 to 500Å.
23. A method for manufacturing a flash memory device, comprising the steps of:
forming a tunnel oxide film and a first polysilicon film on a semiconductor substrate;
forming an oxide film on the first polysilicon film;
nitrifying the top surface of the oxide film by doping an impurity into the oxide film and annealing the oxide film in a nitrogen atmosphere, thereby distributing the impurity along the interface between the first polysilicon film and the oxide film;
forming a dielectric film on the oxide film, and steam-annealing the dielectric film; and
forming a second polysilicon film and a tungsten silicide film over the resulting structure, and performing an etching process thereon.
24. The method of claim 23 , wherein, each step between the step for forming the oxide film and the step for steam annealing the dielectric film, is performed within 12 hours from the preceding step.