Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle
View Patent ↗A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.
1. An information processing device, comprising:
a main processor including general purpose registers to store an operand stack;
a coprocessor including floating point registers to store temporary data;
a data bus to transfer the operand data between the general purpose registers and the floating point registers; and
an accelerator configured to translate a byte code into a native code,
wherein the byte code comprises virtual machine instructions independent of an architecture of the main processor;
wherein the native code comprises translated native instructions dependent on the architecture of the main processor,
wherein the translated native instructions include a first instruction for transferring data from the main processor to the coprocessor, an arithmetic instruction to be executed by the coprocessor, and a second instruction for transferring data from the coprocessor to the main processor,
wherein the accelerator is configured to snoop the operand data being transferred via the data bus by executing the first instruction for transferring data from the main processor to the coprocessor and to detect whether or not the operand data inputted into the coprocessor is unsupported data of the coprocessor before the coprocessor executes the arithmetic instruction, and
wherein the accelerator is configured to detect the unsupported data of the coprocessor and to signal such detection to the main processor before execution of the unsupported data by the coprocessor so that the occurrence of an exception is prevented in the coprocessor,
wherein the accelerator is configured to detect the operation unsupported data in a time period before the coprocessor can detect an exception, and
wherein detection of the unsupported data of the coprocessor is done without the use of an exception handler.
2. The information processing device according to claim 1 ,
wherein the main processor is a central processing unit; and wherein the coprocessor is a floating point processing unit.
3. The information processing device according to claim 1 ,
wherein the accelerator is configured to show agreement with a predetermined numeric value in a time period before the coprocessor can detect an exception.
4. The information processing device according to claim 2 ,
wherein the operation unsupported data is either one of a denormalized number or not-a-number.
5. An information processing device, comprising:
a main processor including general purpose registers to store an operand stack;
a coprocessor including floating point registers to store temporary data ;
a data bus to transfer the operand data between the general purpose registers and the floating point registers; and
an accelerator configured to translate a byte code into a native code,
wherein the byte code comprises virtual machine instructions independent of an architecture of the main processor;
wherein the native code comprises translated native instructions dependent on the architecture of the main processor,
wherein the translated native instructions include a first instruction for transferring data from the main processor to the coprocessor, an arithmetic instruction to be executed by the coprocessor, and a second instruction for transferring data from the coprocessor to the main processor,
wherein the information processing device further comprises means for inhibiting the coprocessor from executing unsupported data, said inhibiting means including means in the accelerator for snooping the operand data being transferred via the data bus by executing the first instruction for transferring data from the main processor to the coprocessor and for detecting whether or not the operand data inputted into the coprocessor is unsupported data of the coprocessor before the coprocessor executes the arithmetic instruction, and
wherein the accelerator further includes means for detecting the unsupported data of the coprocessor and for signaling such detection to the main processor before execution of the unsupported data by the coprocessor so that the occurrence of an exception is prevented in the coprocessor, and
wherein the accelerator is configured to detect the operation unsupported data in a time period before the coprocessor can detect an exception, and
wherein detection of the unsupported data of the coprocessor is done without the use of an exception handler.
6. The information processing device according to claim 5 ,
wherein the main processor is a central processing unit; and
wherein the coprocessor is a floating point processing unit.
7. The information processing device according to claim 5 ,
wherein the accelerator further includes means for showing agreement with a predetermined numeric value in a time period before the coprocessor can detect an exception.
8. The information processing device according to claim 6 , wherein the operation unsupported data is either one of a denormalized number or not-a-number.