IP Library Granted Patent US 7,276,735
Granted Patent B2
US 7,276,735 · App. 10/884,141 · Granted Oct 2, 2007

Laminated semiconductor substrate and optical semiconductor element

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Quick Facts
Patent No.
US 7,276,735
App. No.
10/884,141
Granted
Oct 2, 2007
Kind
B2
Abstract

A low-cost high-property optical semiconductor element for a long wavelength is provided, using a GaAs substrate. The optical semiconductor element comprises a substrate of GaAs having a first surface and a second surface opposite to each other, a buffer layer of In j Ga 1-j As 1-k N k (0≦j≦1, 0.002≦k≦0.05) formed on the first surface of the substrate, a first conductive type clad layer formed on the buffer layer, an active layer formed on the first conductive type clad layer and comprising a well layer of In z Ga 1-z As (0≦z≦1), the well layer having a smaller bandgap than the first conductive type clad layer, the active layer having a thickness of more than its critical thickness for the substrate based upon equilibrium theories, and a second conductive type clad layer formed on the active layer and having a larger bandgap than the well layer.

Claims (30)

1. An optical semiconductor element comprising:

a substrate of GaAs having a first surface and a second surface opposite to each other;

a buffer layer of In j Ga 1-j As 1-k N k (0≦j≦1, 0.002≦k≦0.05) formed on said first surface of said substrate;

a first conductive type clad layer formed on said buffer layer;

an active layer formed on said first conductive type clad layer and comprising a well layer of In z Ga 1-z As (0≦z≦1), said well layer having a smaller bandgap than said first conductive type clad layer, said active layer having a larger thickness than its critical thickness for said semiconductor substrate based upon equilibrium theories;

a second conductive type clad layer formed on said active layer and having a larger bandgap than said well layer; and

a middle layer formed between said buffer layer and said first conductive type clad layer.

2. The optical semiconductor element according to claim 1 , wherein said active layer emits light having a wavelength in the range from 1.25 μm to 1.6 μm by current injection.

3. The optical semiconductor element according to claim 1 , wherein the In composition j of said buffer layer is in the range from 0.05 to 0.30.

4. The optical semiconductor element according to claim 3 , wherein the In composition z of said well layer is in the range from 0.35 to 0.50.

5. The optical semiconductor element according to claim 1 , wherein said well layer has a thickness in the range from 4 nm to 20 nm.

6. The optical semiconductor element according to claim 1 , wherein a lattice mismatch between said substrate and said well layer is not less than 1%.

7. The optical semiconductor element according to claim 1 , wherein lattice mismatch between said substrate and said buffer layer is not more than 2.9%.

8. The optical semiconductor element according to claim 1 , wherein said buffer layer has a thickness in the range from 2 nm to 40 nm.

9. The optical semiconductor element according to claim 1 , wherein said substrate is a first conductive type substrate, and further comprising:

a first electrode formed over said second surface of said substrate so as to electrically connect to said substrate; and

a second electrode formed over said second conductive type clad layer so as to electrically connect to said second conductive type clad layer.

10. The optical semiconductor element according to claim 1 , wherein each of said first and second clad layers has a structure of alternate layers of In t (Ga 1-s Al s ) 1-t As (0≦s≦1, 0≦t≦) and In v (Ga 1-u Al u ) 1-v As (0≦u≦1, 0≦v≦1) for reflecting light emitted by said active layer,

said optical semiconductor element being of a surface emitting type.

11. A laminated semiconductor substrate comprising:

a semiconductor substrate;

a semiconductor layer formed over said semiconductor substrate and having a larger thickness than its critical thickness for said semiconductor substrate based on equilibrium theories, the semiconductor layer comprising a well layer of In z Ga 1-z As (0≦z≦1);

a buffer layer formed between said semiconductor substrate and said semiconductor layer, said buffer layer being made of In j Ga 1-j As 1-k N k (0≦j≦1, 0.002≦k≦0.05);

a first conductive type clad layer formed between said buffer layer and said semiconductor layer and having a larger band gap than said well layer;

a second conductive type clad layer formed on said semiconductor layer and having a larger bandgap than said well layer; and

a middle layer formed between said buffer layer and said first conductive type clad layer.

12. The laminated semiconductor substrate according to claim 11 , wherein a lattice mismatch between said semiconductor layer and said semiconductor substrate is not less than 1%.

13. The laminated semiconductor substrate according to claim 11 , wherein a lattice mismatch between said buffer layer and said semiconductor substrate is not more than 2.9%.

14. The laminated semiconductor substrate according to claim 11 , wherein said semiconductor substrate is made of any one of GaAs, InP, InAs, GaP and Si.

15. The laminated semiconductor substrate according to claim 11 , wherein said buffer layer has a thickness in the range from 2 nm to 40 nm.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2020
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SEOUL SEMICONDUCTOR CO., LTD.
Reel/Frame 052316/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2020
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES AND STORAGE CORPORATION
Reel/Frame 051691/0442 →