IP Library Granted Patent US 7,231,614
Granted Patent B2
US 7,231,614 · App. 10/884,200 · Granted Jun 12, 2007

System and method for design and implementation of integrated-circuit digital filters

Assignee: Quickfilter Technologies, Inc.
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Quick Facts
Patent No.
US 7,231,614
App. No.
10/884,200
Granted
Jun 12, 2007
Kind
B2
Abstract

A system and method for implementing a digital filter, comprising computing on a digital computer a mathematical model of a digital filter; where the mathematical model has a predetermined first set of parameters. The first set of parameters is converted to a second set of parameters, where the second set of parameters includes control parameters for a pre-selected digital-filter integrated circuit (IC). The system then verifies that the execution of the second set of parameters by the digital-filter IC substantially reproduces the behavior of the mathematical model. The verified second set of parameters is then written to permanent storage on the digital-filter IC. The system preferably reads a device-file map characteristic of the particular filter IC intended to be used to implement the filter under design. The converting of the first set of parameters to a second set of parameters further includes computing values corresponding to the second set of parameters that conform to the numerical precision available in the digital-filter IC, and assigning the values so computed to the second set of parameters. The mathematical model of the digital filter is verified by re-computing the model using the second set of parameters.

Claims (47)

1. A method for implementing a digital filter, comprising:

computing on a digital computer a mathematical model of a digital filter; the mathematical model having a predetermined first set of parameters;

converting the first set of parameters to a second set of parameters, where the second set of parameters includes control parameters for a pre-selected digital-filter integrated circuit (IC), where the digital-filter IC has a digital processor for executing arithmetic operations;

verifying that the execution of arithmetic operations on the second set of parameters by the digital-filter IC substantially reproduces the behavior of the mathematical model; and,

writing the verified second set of parameters to permanent storage on the digital-filter IC.

2. The method of claim 1 where the converting of the first set of parameters to a second set of parameters further comprises:

computing values corresponding to the second set of parameters that conform to a numerical precision of the digital processor of the digital-filter IC; and

assigning the values so computed to the second set of parameters.

3. The method of claim 1 where the verifying that the execution of the second set of parameters by the digital-filter IC substantially reproduces the behavior of the mathematical model further comprises re-computing the mathematical model of the digital filter using the second set of parameters.

4. The method of claim 3 further comprising graphically comparing the re-computed mathematical model with the first-computed mathematical model of the digital filter.

5. The method of claim 1 where writing the verified second set of parameters to permanent storage on the digital-filter IC further comprises writing control and coefficient parameters for the digital-filter IC.

6. The method of claim 1 where the converting the first set of parameters to a second set of parameters further comprises reading a device file map.

7. A computer-readable medium having computer executable instructions to be executed by a processor for performing a method comprising:

computing on a digital computer a mathematical model of a digital filter; the mathematical model having a predetermined first set of parameters;

converting the first set of parameters to a second set of parameters, where the second set of parameters includes control parameters for a predetermined digital-filter IC, where the digital-filter IC has a digital processor for executing arithmetic operations;

verifying that the execution of arithmetic operations on the second set of parameters by the digital processor of the digital-filter IC substantially reproduces the behavior of the mathematical model; and,

writing the verified second set of parameters to permanent storage on the digital-filter IC.

8. The computer-readable medium of claim 7 where the converting of the first set of parameters to a second set of parameters further comprises:

computing values corresponding to the second set of parameters that conform to a numerical precision of the processor of the digital-filter IC; and

assigning the values so computed to the second set of parameters.

9. The computer-readable medium of claim 7 where the verifying that the execution of the second set of parameters by the digital-filter IC substantially reproduces the behavior of the mathematical model further comprises re-computing the mathematical model of the digital filter using the second set of parameters.

10. The computer-readable medium of claim 9 further comprising graphically comparing the re-computed mathematical model with the first-computed mathematical model of the digital filter.

11. The computer-readable medium of claim 7 where writing the verified second set of parameters to permanent storage on the digital-filter IC further comprises writing control and coefficient parameters for the digital-filter IC.

12. The computer-readable medium of claim 7 where the converting the first set of parameters to a second set of parameters further comprises reading a device file map.

13. The computer-readable medium of claim 7 further having stored thereon a data structure comprising:

a plurality of fields for the sequential storage of digital filter coefficients;

an input/output control field;

a clock/sample rate field;

a communications interface mode field; and,

an anti-aliasing filter control field.

14. The computer-readable medium of claim 13 further having an analog-to-digital converter control field.

15. The computer-readable medium of claim 13 further having a digital-to-analog converter control field.

16. A computer system comprising, a programmable digital-filter IC, where the digital-filter IC has a digital processor for executing arithmetic operations, a programmable digital computer, and a bus connecting the digital-filter IC and the programmable digital computer;

the digital computer containing instructions for implementing a digital filter, comprising:

computing on the digital computer a mathematical model of a digital filter; the mathematical model having a predetermined first set of parameters;

converting the first set of parameters to a second set of parameters, where the second set of parameters, where the second set of parameters includes control parameters for the digital-filter IC;

verifying that the execution of arithmetic operations on the second set of parameters by the digital-filter IC substantially reproduces the behavior of the mathematical model; and,

writing the verified second set of parameters to permanent storage on the digital-filter IC.

17. The computer system of claim 16 where the converting of the first set of parameters to a second set of parameters further comprises:

computing values corresponding to the second set of parameters that conform to a numerical precision of the processor of the digital-filter IC; and

assigning the values so computed to the second set of parameters.

18. The computer system of claim 16 where the verifying that the execution of the second set of parameters by the digital-filter IC substantially reproduces the behavior of the mathematical model further comprises re-computing the mathematical model of the digital filter using the second set of parameters.

19. The computer system of claim 18 further comprising graphically comparing the re-computed mathematical model with the first-computed mathematical model of the digital filter.

20. The computer system of claim 16 where writing the verified second set of parameters to permanent storage on the digital-filter IC further comprises writing control and coefficient parameters for the digital-filter IC.

21. The computer system of claim 16 where the converting the first set of parameters to a second set of parameters further comprises reading a device file map.

22. The computer system of claim 16 where the digital-filter IC further has an analog-to-digital converter for converting analog input signals.

23. The computer system of claim 16 where the digital-filter IC further has a digital-to-analog converter for outputting analog signals.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2014
From: QUICKFILTER TECHNOLOGIES, LLC
To: GLAST, PHILLIPS & MURRAY, P.C.
Reel/Frame 032145/0278 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2014
From: GLAST, PHILLIPS & MURRAY, P.C.
To: THOMAS, JOHN A.; MILLER, FRED
Reel/Frame 032146/0530 →
RELEASE OF SECURITY INTEREST Recorded Feb 21, 2013
From: ARGONAUT 10 LLC
To: QUICKFILTER TECHNOLOGIES
Reel/Frame 029850/0992 →
SECURITY AGREEMENT Recorded Apr 30, 2009
From: QUICKFILTER TECHNOLOGIES LLC
To: SPINNAKER CAPITAL LLC SECURITY HOLDING AS NOMINEE FOR ARGONAUT 10 LLC; STAIANO, EDWARD
Reel/Frame 022618/0158 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2009
From: QUICKFILTER TECHNOLOGIES INC.
To: QUICKFILTER TECHNOLOGIES, LLC
Reel/Frame 022494/0917 →
SECURITY AGREEMENT Recorded Nov 20, 2008
From: QUICKFILTER TECHNOLOGIES, INC.
To: SPINNAKER CAPITAL LLC SECURITY HOLDING AS NOMINEE FOR ARGONAUT 10 LLC; STAIANO, EDWARD
Reel/Frame 021867/0900 →
RELEASE OF SECURITY INTEREST Recorded Dec 17, 2007
From: ARGONAUT 10 LLC; SORRENTO INVESTMENT GROUP, LLC
To: QUICKFILTER TECHNOLOGIES, INC.
Reel/Frame 020403/0473 →
SECURITY AGREEMENT Recorded Dec 14, 2006
From: QUICKFILTER TECHNOLOGIES, INC.
To: ARGONAUT 10 LLC; SORRENTO INVESTMENT GROUP, LLC
Reel/Frame 018635/0022 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2005
From: BEST, DENNIS R.; SILCO, ROBERT O.
To: QUICKFILTER TECHNOLOGIES, INC.
Reel/Frame 017248/0690 →
Continuity (1)
Related Publication 20060010186A1 · Jan 12, 2006