Impedance matching circuit

1. An impedance matching circuit comprising: a reference impedance; a comparator having a first input coupled to a terminal of the reference impedance having an output and a second input of the comparator coupled to a constant reference voltage; a pull-up counter coupled to an output of the comparator; a pull-up array having a first terminal coupled to a power supply voltage and a second terminal coupled to the terminal of the reference impedance and the first input of the comparator; and a pull-down array having a first terminal coupled to a ground and a second terminal coupled to the first input of the single comparator.

2. The circuit of claim 1 , further including a switch between the terminal of the reference impedance and the first input of the comparator.

3. The circuit of claim 1 , further including a pull-down counter coupled to the output of the comparator.

4. The circuit of claim 3 , further including a switch between the pull-up counter and the output of the comparator.

5. An impedance matching circuit comprising:

a reference impedance having a first terminal coupled to a ground;

a comparator having a first input coupled to a second terminal of the reference impedance and a second input coupled to a constant reference voltage;

a counter/register coupled to an output of the comparator, wherein the counter/register includes a pull-up counter register and a pull-down counter register; and

a first switch between the output of the comparator and the pull-up counter register.

6. The circuit of claim 5 , further including an impedance matching array having a control input coupled to an output of the counter/register.

7. The circuit of claim 6 , wherein the impedance matching array includes a pull-up array and a pull-down array.

8. The circuit of claim 7 , further including a control circuit that selects either the pull-up array or the pull-down array.

9. An impedance matching input buffer comprising:

an impedance matching circuit having a reference impedance and a comparator having a constant reference voltage as an input to the comparator;

a pull-up array coupled to a pull-down array and an input signal, the pull-up array receiving an impedance matching signal from the impedance matching circuit; and

an input buffer having an input coupled to the pull-up array, the pull-down array and the input signal,

wherein the impedance matching circuit has a pull-up counter/register coupled to an output of the comparator and a pull-down counter/register coupled to the output of the comparator.

10. The buffer of claim 9 , wherein the impedance matching circuit has a pull-up array in series with the reference impedance and a switching network coupling the comparator to a node between the pull-up array and the reference impedance.

11. The buffer of claim 9 , wherein the impedance matching circuit includes a pull-up array and a pull-down array.

12. The buffer of claim 11 , wherein the pull-up array of the impedance matching circuit has an impedance that is a predetermined ratio of an impedance of the pull-up array coupled to the input buffer.

13. The buffer of claim 9 , wherein the impedance matching circuit has a first reference impedance and a second reference impedance.