Restricted scan reordering technique to enhance delay fault coverage
Disclosed is a method and apparatus for improved delay fault testing by optimizing the order of scan cells in a scan chain. The order of the scan cells is determined by using a cost value for an order of scan cells, the cost value being computed from costs assigned to orderings of individual pairs of scan cells. These costs can be based on the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain. The disclosed techniques allow for enhanced delay fault coverage by rearranging scan flip-flops without increasing routing overhead.
1. A logic circuit comprising a delay fault testing circuit, said delay fault testing circuit including a scan chain of scan cells, the scan cells in the scan chain being ordered so as to minimize a cost value computed from a plurality of scan cell ordering costs, each scan cell ordering cost assigned to an ordering of a pair of scan cells in the scan chain;
wherein the scan cell ordering cost is based on a number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain.
2. The logic circuit of claim 1 wherein the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain is computed by identifying necessary assignments of initialization and launch patterns of scan cells in the scan chain for every fault in a fault list and by marking the fault as untestable if there is a conflict in the necessary assignments.
3. The logic circuit of claim 2 wherein the necessary assignments of initialization and launch patterns of scan cells in the scan chain are identified from finding necessary assignments for all launch patterns for the fault and, for every scan cell that is assigned a necessary value for the launch pattern, setting the found necessary assignment to each of other scan inputs and forward implying the necessary assignment to internal circuit lines so as to identify conflicts with the necessary assignments of initialization patterns of the fault.
4. The logic circuit of claim 2 wherein the number of faults in the fault list is reduced by pruning the fault list of faults that can be detected independent of scan order.
5. The logic circuit of claim 2 wherein the number of faults in the fault list is reduced by grouping equivalent faults.
6. The logic circuit of claim 1 wherein the scan cells are scan flip-flops.
7. A logic circuit comprising a delay fault testing circuit, said delay fault testing circuit including a scan chain of scan cells, the scan cells in the scan chain being ordered so as to minimize a cost value computed from a plurality of scan cell ordering costs, each scan cell ordering cost assigned to an ordering of a pair of scan cells in the scan chain;
wherein an iterative search is used to find an ordering of the scan cells in the scan chain that minimizes the cost value.
8. The logic circuit of claim 7 wherein only orderings of the scan cells in the scan chain that do not increase routing overhead are considered in the iterative search.
9. A method of testing a logic circuit comprising steps of:
assigning scan cell ordering costs to orderings of pairs of scan cells in a scan chain for a delay fault circuit, each scan cell ordering cost based on a number of faults that are untestable when a pair of scan cells are placed consecutively in the scan chain; and
selecting an ordering of scan cells in the scan chain that minimizes a cost value computed from the scan cell ordering costs so as to enhance delay fault coverage.
10. The method of claim 9 wherein the step of assigning a scan cell ordering cost comprises steps of:
identifying necessary assignments of initialization and launch patterns of scan cells in the scan chain for every fault in a fault list; and
marking the fault as untestable if there is a conflict in the necessary assignments.
11. The method of claim 10 wherein the step of identifying necessary assignments of initialization and launch patterns of scan cells comprises steps of:
finding necessary assignments for all launch patterns for the fault;
for every scan cell that is assigned a necessary value for the launch pattern, setting the found necessary assigning to each of other scan inputs and forward implying the necessary assignment to internal circuit lines so as to identify conflicts with the necessary assignments of initialization patterns of the fault.
12. The method of claim 10 wherein the number of faults in the fault list is reduced by pruning the fault list of faults that can be detected independent of scan order.
13. The method of claim 10 wherein the number of faults in the fault list is reduced by grouping equivalent faults.
14. The method of claim 9 wherein an iterative search is used to select an ordering of the scan cells in the scan chain that minimizes the cost value.
15. The method of claim 14 wherein only orderings of the scan cells in the scan chain that do not increase routing overhead are considered in the iterative search.
16. The method of claim 14 wherein the iterative search is conducted using simulated annealing.
17. The method of claim 9 wherein the scan cells are scan flip-flops.
18. A logic circuit comprising a delay fault testing circuit, said delay fault testing circuit including a scan chain of scan cells, the scan cells in the scan chain being ordered so as to minimize a cost value computed from a sum of a plurality of scan cell ordering costs, each scan cell ordering cost assigned to an ordering of a pair of scan cells in the scan chain and based on a number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain and wherein the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain is computed by identifying necessary assignments of initialization and launch patterns of scan cells in the scan chain for every fault in a fault list and by marking the fault as untestable if there is a conflict in the identified necessary assignments.