IP Library Granted Patent US 7,515,188
Granted Patent B2
US 7,515,188 · App. 10/892,875 · Granted Apr 7, 2009

Method and system for reducing mismatch between reference and intensity paths in analog to digital converters in CMOS active pixel sensors

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Quick Facts
Patent No.
US 7,515,188
App. No.
10/892,875
Granted
Apr 7, 2009
Kind
B2
Abstract

A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied from an active pixel sensor comprises a first and a second pair of switches and a processing circuit. The first pair of switches couple an intensity input node to which the intensity voltage is applied to a first output node and couple a reference input node to which the reference voltage is applied to a second output node during a first operating period. The second pair of switches couple the intensity input node to the second output node and couple the reference input node to the first output node during a second operating period. A polarity reversing circuit is included in the processing circuit for coupling the first and second output nodes to the processing circuit with one polarity during the first operating period and in a reverse polarity during the second operating period.

Claims (29)

1. A circuit for coupling an intensity voltage and a reference voltage from an active pixel sensor to a processing circuit, comprising:

a first pair of switches coupling an intensity input node to which the intensity voltage is applied to a first output node and coupling a reference input node to which the reference voltage is applied to a second output node during a first operating period;

a second pair of switches coupling the intensity input node to the second output node and coupling the reference input node to the first output node during a second operating period; and

a polarity reversing circuit operative to couple the first and second output nodes to the processing circuit with one polarity during the first operating period and in a reverse polarity during the second operating period.

2. The circuit of claim 1 further comprising a toggle switch coupled to the first and second pair of switches, the toggle switch being configured to receive a select signal and operable responsive to the select signal to enable the first pair of switches during the first operating period and to enable the second pair of switches during the second operating period.

3. The circuit of claim 1 further comprising a current mirror circuit included in the processing circuit, the current mirror circuit being configured to receive the reference and intensity voltages and operable to generate an output current representative of the difference between the reference and intensity voltages.

4. The circuit of claim 3 further comprising an A/D converter circuit configured to receive the output current and operable to generate a digital output relative to the output current.

5. A circuit for reducing a mismatch between a reference path and an intensity path coupling a CMOS active pixel sensor to a processing circuit, comprising:

a first and a second transistor coupled to the reference and intensity paths, respectively, and operable to apply a reference and an intensity voltage to a first and second input, respectively, of the processing circuit during a first operating period;

a third and a fourth transistor coupled to the reference and intensity paths, respectively, and operable to apply the reference and intensity voltages to the second and first input, respectively, of the processing circuit during a second operating period;

a toggle switch adapted configured to receive a select signal, and operable responsive to the select signal to enable the first and second transistors during the first operating period and to enable the third and fourth transistors during the second operating period; and

a polarity reversing circuit operable to couple the first and second inputs to the processing circuit with one polarity during the first operating period and in a reverse polarity during the second operating period.

6. The circuit of claim 5 further comprising a current mirror circuit included in the processing circuit, the current mirror circuit being configured to receive the reference and intensity voltages and operable to generate an output current representative of the difference between the reference and intensity voltages.

7. The circuit of claim 6 further comprising an A/D converter circuit configured to receive the output current and operable to generate a digital output relative to the output current.

8. A digital camera comprising:

a CMOS active pixel sensor circuit containing a plurality of pixels connected to a column line, each pixel containing a photo sensing diode and at least one transistor, the photo sensing diode operable to generate an intensity voltage on the column line when light is incident on the pixel and to generate a reference voltage when light is not incident on the pixel; and

a circuit for coupling the intensity and reference voltages to a processing circuit, comprising:

a first pair of switches coupling an intensity input node to which the intensity voltage is applied to a first output node and coupling a reference input node to which the reference voltage is applied to a second output node during a first operating period;

a second pair of switches coupling the intensity input node to the second output node and coupling the reference input node to the first output node during a second operating period; and

a polarity reversing circuit included in the processing circuit, for coupling the first and second output nodes to the processing circuit with one polarity during the first operating period and in a reverse polarity during the second operating period.

9. The digital camera of claim 8 wherein the circuit for coupling the intensity and reference voltages to a processing circuit further comprises a toggle switch coupled to the first and second pair of switches, the toggle switch being configured to receive a select signal and operable responsive to the select signal to enable the first pair of switches during the first operating period and to enable the second pair of switches during the second operating period.

10. The digital camera of claim 9 wherein the circuit for coupling the intensity and reference voltages to a processing circuit further comprises a current mirror circuit included in the processing circuit, the current mirror circuit being configured to receive the reference and intensity voltages and operable to generate an output current representative of the difference between the reference and intensity voltages.

11. The digital camera of claim 10 wherein the circuit for coupling the intensity and reference voltages to a processing circuit further comprises an A/D converter circuit configured to receive the output current and operable to generate a digital output relative to the output current.

12. A method for coupling an intensity voltage and a reference voltage from an active pixel sensor to a processing circuit, the method comprising:

coupling an intensity input node to which the intensity voltage is applied to a first output node and coupling a reference input node to which the reference voltage is applied to a second output node during a first operating period;

coupling the intensity input node to the second output node and coupling the reference input node to the first output node during a second operating period; and

coupling the first and second output nodes to the processing circuit with one polarity during the first operating period and in a reverse polarity during the second operating period.

13. The method of claim 12 further comprising generating an output current representative of the difference between the reference and intensity voltages.

14. The method of claim 13 further comprising generating a digital output relative to the output current.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →