IP Library Granted Patent US 7,235,863
Granted Patent B2
US 7,235,863 · App. 10/893,522 · Granted Jun 26, 2007

Silicon wafer and process for producing it

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Quick Facts
Patent No.
US 7,235,863
App. No.
10/893,522
Granted
Jun 26, 2007
Kind
B2
Abstract

A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ O ⁢ ⁢ i ] < [ O ⁢ ⁢ i ] eq ⁢ ( T ) ⁢ exp ⁢ ⁢ 2 ⁢ σ SiO ⁢ 2 ⁢ Ω r ⁢ ⁢ k ⁢ ⁢ T is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi] eq (T) is a limit solubility of oxygen in silicon at a temperature T, σ SiO2 is the surface energy of silicon dioxide, Ω is a volume of a precipitated oxygen atom, r is a mean COP radius and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least part of the time being exposed to an oxygen-containing atmosphere.

Claims (6)

1. A single-crystal silicon wafer which, down to a depth corresponding to at least 50% of a wafer thickness, has a COP density of less than 10,000 cm −3 and, on its back surface, bears an external getter layer.

2. The silicon wafer as claimed in claim 1 , wherein the external getter layer is a layer which contains silicon oxide, silicon nitride or polycrystalline silicon.

3. A single-crystal silicon wafer which, down to a depth which corresponds to at least 50% of a wafer thickness, has a COP density of less than 10,000 cm −3 and, on its front surface, bears a layer which has been deposited epitaxially or the electrical resistance of which differs from the electrical resistance of a remainder of the silicon wafer.

4. The silicon wafer as claimed in claim 3 , wherein the layer is an epitaxially deposited silicon layer.

5. The silicon wafer as claimed in claim 3 , wherein the layer contains silicon-germanium.

6. The silicon wafer as claimed in claim 3 , wherein the layer contains strained silicon.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →