Interconnection structure and fabrication method thereof
View Patent ↗An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.
1. A method of fabricating an interconnection structure, the method comprising steps of:
forming a first organic low-k material layer over a substrate;
forming a stress redistribution layer on the first organic low-k material layer;
forming a second organic low-k material layer on the stress redistribution layer;
forming an a dual darnascene opening comprising a via opening and a trench in the first organic low-k materiallayer, the stress redistribution layer and the second organic low-k material layer, wherein the via opening passes through the first organic low-k material layer, the stress redistribution layer and a portion of the second organic low-k material layer, and the trench passes througji the other portion of the second organic low-k material layer; and
filling the dual damascene opening with a conductive material for forming an interconnection;
wherein the stress redistribution layer having a heat expansion coefficient close to that of the substrate, and the heat coefficient differs significantly from those of the first and second organic low-k material layers.
2. The method according to claim 1 wherein the stress redistribution layer is formed in between a top portion and bottom portion of the via opening.
3. The method according to claim 1 , wherein the stress redistribution layer includes a silicon nitride layer.
4. The method according to claim 1 , wherein the stress redistribution layer includes a silicon carbide (SiC) layer.
5. The method according to claim 1 , wherein the stress redistribution layer includes a silicon hydroxyl carbide (SiCOH) layer.
6. The method according to claim 1 , wherein the stress redistribution layer includes a spin-on glass (SOG) layer.
7. The method according to claim 1 , wherein the stress redistribution layer includes a hydrido organo siloxane polymer (HOSP) layer.
8. The method according to claim 1 , wherein the first and second organic low-k material layers are made of the same material.
9. The method according to claim 1 , wherein the first and second organic Low-k material layers are made of a material selected from a group consisting of polyimide, fluorinated polyimide, poly(arylene ether), paiylene, polytetrafluoroethylene (PTFE), and benzocyclobutene (BCB).
10. The method according to claim 1 , further comprising a step of forming a cap layer on the substrate before the step of forming a first organic low-k material layer over a substrate.
11. The method according to claim 10 , wherein the cap layer includes a silicon nitride layer.
12. The method according to claim 1 , further comprising a step of forming a diffusion barrier layer over a surface of the opening before the step of filling the opening with a conductive material.
13. The method according to claim 12 , wherein the diffusion barrier layer includes a titanium nitride layer.
14. The method according to claim 1 , wherein the conductive layer includes a copper layer.