IP Library Granted Patent US 7,063,997
Granted Patent B2
US 7,063,997 · App. 10/893,924 · Granted Jun 20, 2006

Process for producing nitride semiconductor light-emitting device

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Quick Facts
Patent No.
US 7,063,997
App. No.
10/893,924
Granted
Jun 20, 2006
Kind
B2
Abstract

A process for producing a nitride semiconductor light-emitting device includes the steps of preparing a substrate, growing a p-type nitride semiconductor layer on the substrate by the MOCVD process using hydrazine-based gas as a nitrogen precursor and N 2 gas as a carrier gas, forming an active layer on the p-type nitride semiconductor layer, forming an n-type conductive nitride semiconductor layer on the active layer, and forming p- and n-electrodes in electrical connection with the p- and n-type nitride semiconductors, respectively.

Claims (36)

1. A process of producing a nitride semiconductor light-emitting device, said process comprising the steps of:

preparing a substrate;

growing a p-type nitride semiconductor layer by the MOCVD (Metal Organic Chemical Vapor Deposition) process using hydrazine-based gas as a nitrogen precursor and N 2 gas as a carrier gas;

forming an active layer on the p-type nitride semiconductor layer;

forming an n-type conductive nitride semiconductor layer on the active layer; and

forming p- and n-electrodes in electrical connection with the p- and n-type nitride semiconductor layers, respectively;

wherein the hydrazine-based, nitrogen precursor gas used in the step of growing the p-type nitride semiconductor layer is a mixed gas additionally containing NH 3 gas, and the amount of the NH 3 gas is less than 50% of the total amount of the mixed gas.

2. The process as set forth in claim 1 , wherein the dopant in the p-type nitride semiconductor layer is Mg.

3. The process as set forth in claim 1 , further comprising the step of:

forming a buffer layer on the substrate, prior to forming the p-type nitride semiconductor layer.

4. The process as set forth in claim 3 , wherein the buffer layer is a low temperature nucleus-growth layer made of Al x In y Ga 1−(x+y) N (0≦x, y≦1) material.

5. The process as set forth in claim 1 , wherein the step of forming the p-type nitride semiconductor layer comprises the steps of forming a first layer made of p-type Al x In y Ga 1−(x+y) N (0≦x, y≦1) material on the substrate, and forming a second layer made of p-type Al x In y Ga 1−(x+y) N (0≦x, y≦1) material having an energy band gap greater than that of the first layer thereon.

6. The process as set forth in claim 1 , wherein the step of forming the n-type nitride semiconductor layer comprises the steps of forming a first layer made of n-type Al x In y Ga 1−(x+y) N (0≦x, y≦1) material on the active layer, and forming a second layer made of n-type Al x In y Ga 1−(x+y) N (0≦x, y≦1) material having an energy band gap smaller than that of the first layer thereon.

7. The process as set forth in claim 1 , wherein the step of forming the n-type nitride semiconductor layer comprises the step of additional forming of a high concentration n-type Al x In y Ga 1−(x+y) N (0≦x, y≦1) layer on the n-type nitride semiconductor layer.

8. The process as set forth in claim 1 , wherein the substrate is an electrically insulative material, and the step of forming the p- and n-electrodes comprises the steps of mesa etching the n-type nitride semiconductor layer and active layer to partially remove a portion thereof so as to expose a region of the p-type nitride semiconductor layer, and forming the p- and n-electrodes on the exposed portion of the p-type nitride semiconductor layer and the n-type nitride semiconductor layer, respectively.

9. The process as set forth in claim 8 , wherein the substrate is selected from the group consisting of sapphire, SiC, ZnO, GaN, GaAs and Si substrates.

10. The process as set forth in claim 8 , wherein the p-electrode includes a Ni/Au layer and the n-electrode includes Ti/Al layer.

11. The process as set forth in claim 1 , further comprising the step of:

forming a p-type contact layer on the substrate, prior to forming the p-type nitride semiconductor layer;

wherein the substrate is an electrically insulative material, and the step of forming the p- and n-electrodes comprises the steps of mesa etching the n-type nitride semiconductor layer and active layer to partially remove a portion thereof so as to expose a region of the p-type nitride semiconductor layer, and forming the p- and n-electrodes on the exposed portion of the p-type nitride semiconductor layer and the n-type nitride semiconductor layer, respectively.

12. The process as set forth in claim 11 , wherein the p-type contact layer is a p-type ZnO layer or p-type InGaN layer.

13. The process as set forth in claim 1 , wherein the substrate is a p-type conductive substrate, and the step of forming the p- and n-electrodes comprises the steps of forming the p-electrode on the lower part of the p-type conductive substrate, and forming the n-electrode on the n-type nitride semiconductor layer.

14. The process as set forth in claim 13 , wherein the substrate is selected from the group consisting of p-type impurities-doped SiC, ZnO, GaN, GaAs and Si substrates.

15. A nitride semiconductor light-emitting device prepared according to the process as set forth in claim 1 .

16. A process of producing a nitride semiconductor light-emitting device, said process comprising the steps of:

preparing an electrically insulative substrate;

forming a p-type contact layer on the substrate;

growing a p-type nitride semiconductor layer on the p-type contact layer by MOCVD process using hydrazine-based gas as a nitrogen precursor and N2 gas as a carrier gas;

forming an active layer on the p-type nitride semiconductor layer;

forming an n-type conductive nitride semiconductor layer on the active layer;

mesa etching the n-type nitride semiconductor layer, the active layer and the p-type nitride semiconductor layer to partially remove a portion of them so as to expose a region of the p-type contact layer; and

forming the p- and n-electrodes on the exposed portion of the p-type contact layer and the n-type nitride semiconductor layer, respectively,

wherein the p-type contact layer is a p-type ZnO layer.

17. The process as set forth in claim 13 , wherein the substrate is selected from the group consisting of p-type impurities-doped ZnO, GaN, and GaAs substrates.

18. The process as set forth in claim 13 , further comprising the step of:

forming a buffer layer on the substrate, prior to forming the p-type nitride semiconductor layer, the buffer layer is a low temperature nucleus-growth layer made of Al x In y Ga 1−(x+y) N (0≦x, y≦1) material.

Assignments (3)
MERGER Recorded Aug 7, 2012
From: SAMSUNG LED CO., LTD.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 028744/0272 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2010
From: SAMSUNG ELECTRO-MECHANICS CO., LTD.
To: SAMSUNG LED CO., LTD.
Reel/Frame 024723/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2004
From: CHO, DONG HYUN; KOIKE, MASAYOSHI; HAHM, HUN JOE
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 015153/0951 →